UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 65

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
[2]
[3]
[4]
[5]
UJA1065_7
Product data sheet
Symbol
Interrupt output; pin INTN
t
Oscillator
f
INTN
osc
vj
=
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
SPI timing is guaranteed for V
so at these lower voltages a lower maximum SPI communication speed must be observed.
t
1 kΩ/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see
δ1 δ3
δ2 δ4
bit
−
40
= selected bit time, depends on LSC bit; 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R
,
,
°
C to +150
=
=
Dynamic characteristics
t
-------------------------------
t
------------------------------- -
bus rec
bus rec
Parameter
interrupt release
oscillator frequency
2 t
2 t
(
(
×
×
°
) min
bit
) max
bit
C; V
(
(
)
)
BAT42
Fig 24. SPI timing
SDO
SCS
SCK
BAT42
SDI
= 5.5 V to 52 V; V
voltages down to 5 V. For V
floating
…continued
X
Conditions
after SPI has read out the
Interrupt register
t
lead
Rev. 07 — 25 February 2010
BAT14
X
t
SCKH
= 5.5 V to 27 V; V
Figure 27
t
su
MSB
T
cyc
BAT42
t
SCKL
MSB
t
h
and
voltages down to 4.5 V the guaranteed SPI timing values double,
High-speed CAN/LIN fail-safe system basis chip
Figure
BAT42
28.
[1]
≥
V
BAT14
Min
2
460.8
−
1 V; unless otherwise specified. All
t
DOV
Typ
-
512
LSB
t
lag
LSB
UJA1065
© NXP B.V. 2010. All rights reserved.
Max
-
563.2
t
SSH
1
/R
001aaa405
floating
2
/C
X
1
):
65 of 76
kHz
Unit
μs