UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 25

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

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NXP Semiconductors
UJA1065_7
Product data sheet
6.8.6.1 TXDL dominant clamping
6.8.6.2 LIN dominant clamping
6.8.6.3 LIN recessive clamping
6.8.4 LIN slope control
6.8.5 LIN driver capability
6.8.6 Bus and TXDL failure detection
6.9 Inhibit and limp-home output
During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN
provides an internal switch to BAT42. For master and slave operation an external resistor,
1 kΩ or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external
diode in series with the termination resistor is not required due to the incorporated internal
diode.
The LSC bit in the Physical Layer Control register offers a choice between two LIN slope
times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).
Setting the LDC bit in the Physical Layer Control register will increase the driver capability
of the LIN output stage. This feature is used in auto-addressing systems, where the
standard LIN 2.0 drive capability is insufficient.
The SBC handles and reports the following LIN-bus related failures:
These failure events force an interrupt to the microcontroller whenever the status changes
and the corresponding interrupt is enabled.
If the TXDL pin is clamped dominant for longer than t
disabled. After the TXDL pin becomes recessive the transmitter is reactivated
automatically when detecting bus activity or manually by setting and clearing the LTC bit.
When the LIN-bus is clamped dominant for longer than t
t
If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter
is disabled. The transmitter is reactivated automatically when the LIN bus becomes
dominant or manually by setting and clearing the LTC bit.
The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for
an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via
the ILEN bit and ILC bit in the System Configuration register; see
TXDL(dom)(dis)
•
•
•
LIN-bus shorted to ground
LIN-bus shorted to V
TXDL clamped dominant; the transmitter is disabled
), the state of the LIN termination is changed according to
Rev. 07 — 25 February 2010
BAT14
or V
BAT42
High-speed CAN/LIN fail-safe system basis chip
; the transmitter is disabled
TXDL(dom)(dis)
LIN(dom)(det)
Figure
the LIN transmitter is
(which is longer than
UJA1065
Figure
© NXP B.V. 2010. All rights reserved.
13.
12.
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