UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 45

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
6.14.2 Forced normal mode
There are two possibilities to enter Software development mode. One is by setting the
ISDM bit via the Special Mode register; possible only once after a first battery connection
while the SBC is in Start-up mode. The second possibility to enter Software development
mode is by applying the correct V
applied to pin BAT42.
To stay in Software development mode the SDM bit in the Mode register has to be set with
each Mode register access (i.e. watchdog triggering) regardless of how Software
development mode was entered.
The Software development mode can be exited at any time by clearing the SDM bit in the
Mode register. Reentering the Software development mode is only possible by
reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.
For system evaluation purposes the UJA1065 offers the Forced normal mode. This mode
is strictly for evaluation purposes only. In this mode the characteristics as defined in
Section 9
In Forced normal mode the SBC behaves as follows:
Forced normal mode is activated by applying the correct V
TEST pin during first battery connection.
•
•
•
•
•
•
•
•
•
•
•
•
•
SPI access (writing and reading) is blocked
Watchdog disabled
Interrupt monitoring disabled
Reset monitoring disabled
Reset lengthening disabled
All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than
t
V1 is started with the long reset time t
performed until V1 is restored (normal behavior), and the SBC stays in Forced normal
mode; in case of an overload at V1 > t
V2 is on; overload protection active
V3 is on; overload protection active
CAN and LIN are in Active mode and cannot switch to Off-line mode
INH/LIMP pin is HIGH
SYSINH is HIGH
EN pin at same level as RSTN pin
V1(CLT)
and
Section 10
Rev. 07 — 25 February 2010
cannot be guaranteed.
th(TEST)
High-speed CAN/LIN fail-safe system basis chip
input voltage at pin TEST before the battery is
RSTNL
V1(CLT)
. In case of a V1 undervoltage, a reset is
Fail-safe mode is entered
th(TEST)
input voltage at the
UJA1065
© NXP B.V. 2010. All rights reserved.
45 of 76