PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 20

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

The following SCI configurations are fixed and cannot be set by the microcontroller:
Recommendation for configuring: Set CRC, automatic acknowledgement and clock
gating to ´on´.
The maximum possible SCI clock frequency is 6 MHz for point to point applications (full
duplex) and about 2 MHz for multipoint to multipoint applications, dependent on the
electrical capacity of the bus lines of the PCB.
Figure 11
Figure 11
Every write into or read from a register of the OctalFALC
message CMD from the Host (microconroller) and is then confirmed by an acknowledge
message ACK from the OctalFALC
acknowledgement is set (bit ACK_EN, see
The frame structure of this messages are shown in
In general the LSB of every byte is transmitted first and lower bytes are transmitted
before higher bytes (regarding the register address).
The HDLC flags mark beginning and end of all messages.
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for
addressing. The bit C/R (Command/Response) distinguishes between a command and
a response. The bit MS (Master/Slave) is ´0
Table 5
The source address is defined by pinstrapping of A5 to A0 after reset, but other values
can be configured by programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which
distinguish between the different kind of commands, see
address and the 8 bit wide data whereas the read CMD payload includes only the control
bits and the register address. Register addresses can be either OctalFALC
Delta Sheet
– Interrupt feature is disabled, bit INT_EN = ´0
– Arbitration always made with LAPD (only SCI applications like in
Figure 10
and
shows the message structure of the OctalFALC
Figure
SCI Message Structure of OctalFALC
are possible), bit ARB = ´0
12.
HOST
CMD
ACK
TM
20
B
Table
B
´
´ for all Slaves and ´1
if in the SCI configuration automatic
OctalFALC
OctalFALC_SCI_message_structure
5).
B
´
Figure
TM
Table
TM
TM
12.
.
is initiated by a command
4, the 14 bit wide register
B
´ for all masters, see
Rev. 2.0, 2005-05-03
Serial Interfaces
OctalFALC
PEF 22558 E
Figure 9
TM
register
and
TM