PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 32

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

Table 8
Reset Pin
5.7
If the central clock PLL status indication bit GIS2.PLLLS changes, an interrupt is
generated. An additional bit GIS2.PLLLC is provided to indicate the change. Masking
can be made by GIMR.PLLL. The visibility of PLLLC can be set by the register bit
IPC.VISPLL.
For COMP = ´1´ both of the pseudo QuadFALC®s have its own (interrupt) status register
GIS2 and mask register GIMR. The status of the one PLL is “doubled” for the two status
registers . So masking or setting of the visibility can be made Individulally in both of the
pseudo QuadFALC®s.
The status bit PLLLS is only available for COMP = ´1´, but the status of the PLL is shown
in GIS2.PLLLS independent on the value of COMP.
.
Delta Sheet
inactive
PLL Interrupt Status Bits
Conditions for a PLL Reset (cont’d)
GCM2.VFREQ_EN
0 -> 1
1 -> 0
or
1
0
32
Used controller
interface
(Motorola or Intel)
(Motorola or Intel)
(Motorola or Intel)
SCI or SPI
SCI or SPI
SCI or SPI
asynchron
asynchron
asynchron
A PLL reset is
made...
That is not allowed
are written and their
if actual values of N
GCM6 are different
if pinstrap values in
of the “fixed mode”
to internal settings
internal settings of
if GCM5 or GCM6
the “fixed mode”.
or M in GCM5 in
Rev. 2.0, 2005-05-03
values change
values change
are different to
values N or M
if pinstrappng
if pinstrappng
OctalFALC
changes
PEF 22558 E
Clock Modes
never
TM