PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 31

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

serial interfaces, the clock MCLK must be active and must have a defined frequency
before reset becomes inactive. Depending on the supplied MCLK frequency the internal
PLL must be configured if the SCI- or SPI-Interface mode is selected by IM(1:0). This
can be performed either
•
•
The configuration of the PLL by pinstrapping in case of serial interface modes is done in
the same way as by using the registers GCM5 and GCM6 if asynchronous micro
controller interface mode (Intel or Motorola) is selected. Calculation of the values to be
configured by pinstrapping can be done also by using the formulas described for the
registers GCM6 or by using the “flexible Master Clock Calculator” which is part of the
software support of the OctalFALC
of D(15:5) configures the PLL directly, so changes causes a direct reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in
of the PLL causes a reset of the clock system.
Table 8
Reset Pin
Delta Sheet
Or by usage of the ”clocking fixed mode” (GCM2.VFREQ_EN = ´0´). This is only
allowed if the values of N and M defined by pinstrapping are identical to that
values which are internally used for the “clocking fixed mode”. This avoids
changing of N and M by switching into the ”clocking fixed mode” and therefore a new
reset of the PLL. (A reset of the PLL can cause a reset of the hole transceiver! Clock
and data processing will be interrupted.) The used values of N and M in “clocking
fixed mode” are: N = ´33
be: D(10:5) = ´HLLLLH´, D(15:11) = ´LLLLL´. In ”clocking fixed mode” further
programming of the registers GCM1 to GCM8 is no longer necessary. The
pinstrapping configuration at the pins D(15:5) do not have any effect. Changing of
these values does NOT cause a reset of the PLL. Switching between E1 and T1
modes causes a reset of the clock unit but not of the main PLL itself.
By strapping of the pins D(15:5) if “flexible master clocking mode” is enabled
(GCM2.VFREQ_EN = ´1´). Because the “flexible master clocking mode” is enabled
after reset, pinstrapping at D(15:5) is always necessary! Every status change of the
signals at these pins causes a reset of the PLL. Configuring by the registers GCM5
and GCM6 has no effect and does not cause a reset of the main PLL
active
Conditions for a PLL Reset
GCM2.VFREQ_EN
(will be set to ´1´by
10
´, M = ´0
reset
x
TM
. If the serial interfaces are selected, pinstrapping
10
´. This requires the pinstrapping configuration to
31
Used controller
interface
x
A PLL reset is
made...
Table
Rev. 2.0, 2005-05-03
OctalFALC
PEF 22558 E
always
Clock Modes
8. Every reset
TM