PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 37

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

TM
OctalFALC
PEF 22558 E
HDLC/BOM Controllers
8
HDLC/BOM Controllers
Each of the eight ports provides three HDLC/BOM Controllers. Each of these units can
be attached to either the line side (“standard”) or the system side (“inverse”). Inverse
HDLC mode is selected by setting MODE.HDLCI = 1, MODE2.HDLCI2 = 1, or
MODE3.HDLCI3 = 1 (for each of the three HDLC controllers and each of the eight
E1/T1/J1 ports individually). Note that a detection of a Out-Band loop message (BOM
code) on the line side is only possible if the HDLC controller is attached to the line side;
a detection of a BOM code on the system side is only ossible in the “inverse” mode of
the HDLC controller.
Each HDLC/BOM controller can be reset individually without disturbing the transmission
on the remaining channels. Use CMDR.SRES for HDLC channel 1, CMDR3.RRES and
CMDR3.SRES for HDLC channel 2, and CMDR4.RRES and CMDR4.SRES for HDLC
channel 3, respectively.
Each of the eight ports provides one signalling controller for SS7 signaling.
The signalling controller has an interrupt status bit ISR1.SUEX which shows exceeding
of the error threshold in SS7 mode. These interrupt status bit is masked by the bit
IMR1.SUEX .
The error counter for SS7 mode can be reset by setting the register bit CMDR2.RSUC.
The error threshold for SS7 mode can be configured by setting the register bit
CCR5.SUET.
After an RDO interrupt on one HDLC controller, the receive HDLC controller needs no
reset. So a receive HDLC controller reset per channel is not necessary.
Note: CMDR.RRES resets the whole RX path and therefor all HDLC channels.
The FIFO depth is doubled to 128 byte in RX, see
Table
9, and 128 byte in TX (by setting
register bit CCR2.TFTS) per HDLC/BOM controller (64 byte user and 64 byte shadow
RAM).
As in the FALC56 version V2.1 the total length of the received frame can be always read
directly in registers RBCL and RBCH after a RPF interrupt, except when the threshold is
increased during reception of that frame, but additionally to the FALC56 version V2.1 bit
RBC5 will be taken into account if the FIFO depth is 64 bytes, see
Table 9
as example
for the HDLC channel 1. The register bits CCR3.RFT(2:0)2 and CCR4.RFT(2:0)3 set the
FIFO depth in the same way for the HDLC channel 2 and 3 respectively.
If a HDLC frame was completely received the content of the register RSIS (HDLC
channel1, RSIS2 andRSIS3 for HDLC channel 2 and 3) will be written as last byte into
the receive FIFO.
Delta Sheet
37
Rev. 2.0, 2005-05-03