PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 6

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Delta Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Basic Operation Modes for Microcontroller interface . . . . . . . . . . . . . . 10
Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Intel Non Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . 14
Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SCI interface Application with Point to Point Connections . . . . . . . . . . 19
SCI interface Application with Multipoint to Multipoint Connection . . . 19
SCI Message Structure of OctalFALC
Frame Structure of OctalFALC
Principle of Building of Addresses and RSTA Bytes in the SCI ACK
Message 22
SCI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Receive Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Principle of Setting Parameters of the DCO-X and DCO-R . . . . . . . . . 29
Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXRA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Standard DL-Bit Access in ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
Optional DL-Bit Access in ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
HDLC Controller Standard Configuration for all three HDLC Channels 38
HDLC Controller Inverse Configuration for All Three HDLC Channels 38
Principle of System Interface Multiplex Modes, shown for RDO . . . . . 40
Redundancy Application (shown for one channel and using RLM) . . . 43
Long Haul Redundancy Application using the Analog Switch (shown for
one line) 44
Transmit Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Receiver Configuration with Integrated Analog Switch for Receive
Impedance Matching 49
GIS Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VSTR and DSTR Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . 63
Principle of configuration of SEC/FSC Output . . . . . . . . . . . . . . . . . . . 64
PG-LBGA-256-1 (Plastic Green Low Profile Ball Grid Array Package) 84
6
TM
SCI Messages. . . . . . . . . . . . . . . . . 21
TM
. . . . . . . . . . . . . . . . . . . . . . . 20
Rev. 2.0, 2005-05-03
OctalFALC
PEF 22558 E
Page
TM