PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 30

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

•
For the calculation for the appropriate register settings the “flexible Master Clock
Calculator” can be used which is part of the software support of the OctalFALC
All required clocks for E1 or T1/J1 operation are generated by the device internally. The
global setting depends only on the selected master clock frequency and is the same for
E1 and T1/J1 because both clock rates are provided simultaneously.
To meet the E1 requirements the MCLK reference clock must have an accuracy of better
than ± 32 ppm. The synthesized clock can be controlled on pins RCLK, SCLKR and
XCLK.
Figure 20
If the (asynchronous) microcontroller interface mode is selected by IM(1:0) the PLL must
be configured either
•
•
The SPI and SCI are synchronous interfaces and therefore need defined clocks
immediately after reset, before any device configuration is done. To enable access to
Delta Sheet
registers GCM(8:1) accordingly, see formulas in GCM6 description. All eight ports
can work in E1 or T1 mode individually. After reset the clocking unit is in “flexible
master clocking mode”.
In the “clocking fixed mode” (GCM2.VFREQ_EN = ´0´) the tuning of the clocking unit
is done internally so that no setting of the global clock mode registers GCM(8:1) is
necessary. All eight ports must work together either in E1 or in T1 mode.
By programming of the registers GCM5 and GCM6 in “flexible master clocking
mode”. Every change of the contents of these registers - the divider factors N and M
of the PLL - causes a reset of the PLL. Switching between E1 and T1 modes in
arbitrary channels causes a reset of the clock unit but not of the PLL itself.
Or by enabling of the ” fixed mode”: GCM2.VFREQ_EN = ´0´. Programming of
registers GCM5 and GCM6 is not necessary. Any programming of GCM5 and GCM6
does NOT cause a reset of the PLL. Switching between E1 and T1 modes (for all
channels) causes a reset of the clock unit but not of the PLL itself.
MCLK
D(15:5)
Flexible Master Clock Unit
PLL
IM(1:0)
Flexible Master Clock Unit
GCM1...GCM8
30
E1 Clocks
T1 / J1
Clocks
Rev. 2.0, 2005-05-03
OctalFALC
PEF 22558 E
Clock Modes
O c talFA LC __F0116
channel
1 to 8
TM
.
TM