PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 28

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

TCLK loss is detected if the transmit clock derived from TCLK failed to occur.
Automatic transmit clock switching is controlled by the register bit CMR4.ATCS.
If the TCLK input is used directly as transmit clock XCLK, the output of the DCO-X (CU-
ADPLL-X) is not used. The DCO-X reference clock is SCLKX. If loss of TCLK is detected,
the transmit clock will be switched automatically to the DCO-X output which is
synchronous to SCLKX if CMR4.ATCS = ´1´. This switching is shown in the interrupt
status bit ISR7.XCLKSS0 which is masked by IMR7.XCLKSS0. This switching cannot
be done in general without occuring of phase jumps or spikes in the transmit clock XCLK.
Additionally after loss of TCLK the transmit clock XCLK is also lossed during the
“detection time” for loss of TCLK,
If the transmit clock XCLK is sourced by the DCO-X output and the DCO-X reference
clock is TCLK, the DCO-X reference will be switched to SCLK after a loss of TCLK was
detected if CMR4.ATCS = ´1´. This switching is shown in the interrupt status bit
ISR7.XCLKSS1 which is masked by IMR7.XCLKSS1.
In that case, the transmit clock XCLK fullfils the jitter-, wander- and frequency deviation-
requiements as specified for E1/T1 after the clock source of the DCO-X was changed.
Slipping of the (active) transmit buffer should be avoided.
Comment: TCLK is sourced by RCLK in normal application, so loss of TCLK happens
because of loss of RCLK.
5.3
TCLK supports 1.544, 3.088, 6.176, 12.352 and 24.704 MHz in T1/J1 mode and 2.048,
4.096, 8.192, 16.384 and 32.768 MHz in E1 mode and in T1/J1 channel translation
mode. If COMP = ´0´controlling is done by the register CMR5, bits STF(2:0), if COMP =
´1´ controlling is done by the register CMR1, bit STF.
5.4
RCLK supports 1.544, 3.088, 6.176, and 12.352 in T1/J1 mode and 2.048, 4.096, 8.192,
and 16.384 MHz in E1 mode and in T1/J1 channel translation mode. If COMP =
´0´controlling is done by the register CMR4, bits RS(1:0), if COMP = ´1´ controlling is
done by the register CMR1, bits RS(1:0). If the recovered clock out (of the clock data
recovery) is the source of RCLK then only 2.048 MHz (1.544,) is possible. If the DCO-R
is the source of RCLK all above described frequencies are possible.
5.5
The corner frequencies of DCO-R and DCO-X can be adjusted in a wider range.
Proposal: The DCO-X and the DCO-R (2nd order PLLs) must have eigenfrequencies in
the range 8 Hz to 0.2 Hz, for example 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz, 0.25 Hz, 0.125 Hz
Delta Sheet
TCLK Frequency
RCLK Frequency
DCO-R/DCO-X Characteristics
28
Rev. 2.0, 2005-05-03
OctalFALC
PEF 22558 E
Clock Modes
TM