PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet - Page 39

• Manufacturer Part Number: PEF22558EV11GXP
• Manufacturer: Lantiq

Specifications of PEF22558EV11GXP

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

Switchin between HDLC and BOM (if both MODE.BRAC and MODE.HRAC are set) will
be done in the following way:
•
•
•
•
The status bit SIS.BOM reflects the actual mode of the HDLC/BOM controller.
Note that BOM codes ´7E
If a BOM message occurs “inside” of a HDLC protocoll, the HDLC protocoll (frame) is
corrupted.
9
9.1
The following multiplex modes are supported, see
ports are shown, and
•
•
•
Switching between 8-to-1 Multiplex Mode (using only one port) and QuadFALC
compatible 4:1 Multiplex Modes (using two or more ports) is done by the register bit
GPC6.SSI16, see
Multiplexing of RSIG is done in the same way as shown for RDO in
Demultiplexing of XDI and XSIG is done vice versa.
Delta Sheet
After reset the HDLC/BOM controller is in HDLC mode
After eight consecutive ones (´FF
that eight consecutive ones are also an HDLC abort)
After one HDLC flag (´7E
additionalHDLC flags are not necessary)
Asequence ´FF
8-to-1 Multiplex Mode at 16 Mbit/s. Multiplexing is done on port 1. Output pins of the
other ports are set to tristate input pins of the other ports are unused.
Dual 4-to-1 Multiplex Mode at 8 Mbit/s. Multiplexing is done on port 1 and port 5.
Output pins of the other ports are set to tristate , input pins of the other ports are
unused.
Dual 4-to-1 Multiplex Mode at 16 Mbit/s. Multiplexing is done on port 1 and port 5
were four phases are unused on every port. Disjunct phases must be used on both
ports. 16 Mbit/s multiplexing is done by external logical or on the PCB. Output RDO
is driven to low level for inactive phases. Output pins of the other ports are undefined,
input pins of the other ports are unused.
System Interface
System Multiplex Mode
Table
H
´, ´7E
Table
10.
H
H
´ are seen also as HDLC start flag
‘ should be avoid.
10:
H
´) was received: switching to HDLC mode (directly,
H
´) were received: switching to BOM mode (note
39
Figure
26, were only pins RDO of the
Rev. 2.0, 2005-05-03
System Interface
OctalFALC
PEF 22558 E
Figure
26.
TM
®