WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 109

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.1
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 60. Intel
Figure 19. Intel
Intel
Table 60
Figure 19
Master Clock Timing
Master clock (MCLK) frequency
Master clock tolerance
Master clock duty cycle
Output Transmit Timing
Pulse width
Delay time: OE low to driver high impedance
Delay time: TCLK low to driver high
impedance
TCLK, TPOS, TNEG Timing
TCLK frequency
TCLK average tolerance when using JA in
transmit path
TCLK tolerance
TCLK burst rate
TCLK duty cycle
TPOS/TNEG pulse width (RZ mode)
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
®
®
®
LXT385 Transceiver Transmit Timing Characteristics
LXT385 Transceiver - Transmit Timing
lists transmit timing characteristics for the LXT385 ransceiver.
LXT385 Transceiver Timing
TNEG
is a transmit timing diagram for the LXT385 ransceiver.
TPOS
TCLK
Parameter
tSUT
Intel
Sym.
t
SUT
t
HT
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Min.
219
236
-50
-50
-50
40
50
10
20
20
tHT
2.048
2.048
Typ.
244
60
Max.
+50
+50
+50
269
252
60
75
20
90
1
MHz
MHz
MHz
Unit
ppm
ppm
ppm
ns
μs
μs
ns
ns
ns
%
%
Gapped
transmit clock
NRZ mode
RZ mode
(TCLK = High
for >16 MCLK
clock cycles)
Condition
Test
109