WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 78

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.4.2
78
Intel
Figure 14. Host Processor Mode - Serial Interface Read Timing
SCLK
®
SDO
CS
SDI
LXT385 Octal E1 S/H PCM Transceiver with JA
R/W = 1: Read operation
R/W = 0: Write operation (SDO remains high impedance)
R/W
Host Processor Mode - Serial Interface
A Host Processor mode with a serial interface consisting of the CS, SCLK, SDI, and SDO pins is
selected by connecting the MODE pin to a voltage that is equal to 1/2 VCC (which can be
accomplished by connecting one 10k Ω resistor to VCC and a second 10k Ω resistor to ground).
Figure 14
accessible through a 16-bit word consisting of the following:
•
•
An 8-bit Address/Command byte.
A subsequent 8-bit Data byte. (Depending on the R/W state, the D0-D7 values are valid on
either SDI or SDO, but never are the D0-D7 values valid on both SDI and SDO.)
A1
— The signal on the R/W pin determines whether a read or a write operation occurs.
— The signals on pins A1-A5 go to an address decoder that decodes an address. (The address
— When R/W = 0, D0-D7 on SDO are don’t cares. The D0-D7 values on SDI are active,
— When R/W = 1, the D0-D7 values on SDO are active, with valid data that theLXT385
decoder ignores signals on the A6 and A7 pins.)
with valid data being written to theLXT385 ransceiver.
ransceiver writes to the host processor. The D0-D7 values on SDI are don’t cares.
Address / Command Byte
shows timing for the host processor interface when it is in serial mode. Registers are
A2
High Impedance
A3
A4
A5
(Don't
care)
A6
(Don't
care)
A7
D0
D0
D1
D1
Input (Write) Data Byte
Output (Read) Data Byte
D2
D2
D3
D3
D4
D4
D5
D5
Revision Date: 19-Jan-2006
Document Number: 249252
D6
D6
Revision Number: 006
D7
D7