WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 37

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 9.
Framer/Mapper Transmit Signals (Sheet 1 of 3)
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
Signal
Name
QFP
100
107
Pin
74
81
29
36
2
9
PBGA
Ball
D14
B14
N14
L14
D1
N1
B1
L1
Signal
Type
DI
Intel
Transmit Clock Input 7:0.
When the LXT385 ransceiver is in Hardware mode and
TCLK is:
)
NOTE: When the LXT385 ransceiver is in the Host
When pulse shaping is disabled, it is possible to overheat
and damage the LXT385 ransceiver by leaving transmit
inputs high continuously. For example a programmable
ASIC might leave all outputs high over an extended period,
until it is programmed. To prevent this, clock one of these
signals: TPOS, TNEG, TCLK, or MCLK. Another solution is
to set one of these signals low: TPOS, TNEG, TCLK, or OE.
Note: The TAOS generator uses MCLK as a timing
• Operating withthe normal clock signal, TPOS and
• Low and remains in a low state, the transmitter output
• High (for more than 16 consecutive MCLK clock
®
LXT385 Octal E1 S/H PCM Transceiver with JA
TNEG are sampled on the falling edge of TCLK.
drivers enter a low-power high-impedance tristate.
cycles), and MCLK is:
• operating normally as a clock, the LXT385 ransceiver
• not operating as a clock, but is either low or high, the
enters the TAOS mode. (For details, see
“Transmit All Ones
pulse-shaper circuit shown in
For information on how to prevent damage to the
LXT385 ransceiver when pulse shaping is disabled,
see
reference. In order to assure that the output
frequency is within specification limits, MCLK must
have the applicable stability.
Normal Clock
Processor mode, TAOS mode can be selected
using registers in
MCLK cycles
MCLK cycles
consecutive
consecutive
High for 16
High for 16
Section 6.4.2, “Transmitter Pulse
TCLK
Low
Signal Description
Normal
high or
MCLK
Operations”.
Either
Don’t
Don’t
Clock
Chapter 8.0,
care
care
low
TNEG and TPOS
sampled on falling
edge of TCLK
Transmitter driver
outputs enter high-
impedance tristate
Disables transmit
pulse shaping
TAOS
Figure 1
“Registers”.
Result
Shaping”.)
is disabled.
Section 6.8,
37