WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 79

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.5
7.5.1
7.5.2
7.5.3
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Note:
Interrupt Handling
Interrupt Sources
Interrupt sources include the following:
Interrupt Enable
The LXT385 ransceiver provides a latched interrupt output (INT). An interrupt occurs any time
there is a transition on any enabled bit in the corresponding status register.
Register 06h
Interrupt Enable register. Writing a logic ‘1’ into the corresponding mask register enables a bit in
the corresponding interrupt status register to generate an interrupt. The power-on default value is
all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers.
Register 08h
Interrupt Status register. When there is a transition on any enabled bit in a status register, the
associated bit of the interrupt status register is set and an interrupt is generated (if one is not already
pending). When an interrupt occurs, the INT pin is asserted low. The output circuitry of the INT pin
consists of an active pull-down device (an open drain). An external pull-up resistor of
approximately 10kΩ is required to support wired-OR operation with other LXT385 ransceivers.
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) operates as follows:
1. Status change in the LOS (Loss of Signal) Status register (04h,
2. Status change in the AIS (Alarm Indication Signal) Status register (13h,
1. The ISR must read the interrupt status registers (08h and 15h) to identify the interrupt source.
2. The ISR must then read the corresponding status monitor register to obtain the current status of
•
•
ransceiver continuously monitors the receiver signal and updates the specific LOS status bit to
indicate either the presence or absence of an LOS condition.
(Loss of Signal) Status register (04h,
Table
AIS status bit to indicate either the presence or absence of a AIS condition.
the LXT385 ransceiver.
Reading an interrupt-status register clears the ‘sticky’ status bit set by the interrupt. (A ‘sticky’
status bit is a bit that, once set, remains set until it is explicitly cleared.) Automatically clearing
an interrupt-status register prepares the register for the next interrupt.
The status-monitor registers are the LOS Status register (04h,
register (13h,
on the rising edge of the read or data strobe. When all pending interrupts are cleared, the signal
on INT goes high.
29). The LXT385 ransceiver monitors the incoming data stream and updates the specific
(Table
(Table
Table
33) is the LOS Interrupt Status register, and register 15h
31) is the LOS Interrupt Enable register, and register 14h
44). Reading a status-monitor register clears its corresponding interrupts
Table
Intel
®
29). The LOS (Loss of Signal) Status register (04h,
LXT385 Octal E1 S/H PCM Transceiver with JA
Table
Table
29)and the AIS Status
29). The LXT385
(Table
Table
(Table
46) is the RAIS
44). The LOS
45) is the AIS
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