WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 85

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WJLXT385LE.B1

Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT385LE.B1

Lead Free Status / RoHS Status
Supplier Unconfirmed
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 35. Reset Register, RES - 0Ah
Bit
7:0
RES7:0
Name
Reset.
The RES7:0 bits are used to set all LXT385 ransceiver registers to their default
values.
For details on non-multiplexed and multiplexed modes, see
Processor
• Except when using an Intel
• When using Intel
to this field initiates a 1-microsecond software reset cycle.
extend the software reset cycle time to 2 microseconds. (For more
information on the software reset cycle when using an Intel
non-multiplexed mode, see
Interface”.)
Modes”.
®
processor in a non-multiplexed mode, to use this field
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
®
Section 7.4.1, “Host Processor Mode - Parallel
Description
processor in a non-multiplexed mode, writing
Section 7.4, “Host
®
processor in a
R/W
R/W
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