WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 66

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

66
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
When the LXT385 ransceiver is in the:
For information on jitter attenuation as it applies specifically to the receiver, see
Attenuation”.
Standard jitter-attenuation recommendations and specifications that the LXT385 ransceiver JA
meets are the following. (For more recommendations and specifications, see
“Recommendations and
•
•
•
•
•
Host Processor mode:
Hardware mode:
European Telecommunications Standards Institute (ETSI) publication, ETSI CTR12/13
International Telecommunication Union (ITU) publications:
BAPT220
— The Global Control Register (GCR,
— Depending on the GCR register FIFO64 bit setting, the depth of the FIFO used in the JA is
— The low-limit jitter attenuator corner frequency depends on the FIFO depth and the JACF
— The JASEL pin determines whether JA is positioned in the receive or transmit path.
— The FIFO length is fixed to 64 bits.
— The low-limit jitter attenuator corner frequency is fixed to 3.5 Hz. (For more information
— ITU-T G.736
— ITU-T G.742, when used with the SXT6234 E2-E1 mux/demux.
— ITU-T G.783, combined jitter when used with the SXT6251 21E1 mapper.
positioned in the receive or transmit path.
either a 32 x 2-bit FIFO or a 64 x 2-bit FIFO. (For FIFO64 bit details, see
Chapter 8.0,
bit setting in the GCR register. (For JACF bit details, see
“Registers”.)
on the JA corner frequency,
“Registers”.)
Specifications”.)
seeTable 70
Table
in
40) JASEL bits determine whether the JA is
Chapter 14.0, “Jitter
Table 40
Performance”.)
in
Chapter 15.0,
Revision Date: 19-Jan-2006
Document Number: 249252
Chapter 8.0,
Section 6.6, “Jitter
Revision Number: 006
Table 40
in