WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 30

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.2
30
Intel
Table 7.
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Note:
Microprocessor-Standard Bus and Interface Signals
Table 7
ransceiver.
For multi-function pins, the pin name in
For information on selecting parallel or serial interfaces, see the signal description for MODE in
Section 5.6, “Configuration and Mode-Select
Microprocessor-Standard Bus and Interface Signals (Sheet 1 of 3)
A4
A3
A2
A1
A0
ACK
SDO
ALE
SCLK
ALE /
SCLK
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
Signal
Name
/ AS /
/ RDY /
AS
lists and describes the microprocessor-standard bus and interface signals for the LXT385
/
QFP
Pin
12
13
14
15
16
83
86
86
PBGA
Ball
K14
J12
J12
G3
F4
F3
F2
F1
Signal
Type
DO
DI
DI
DI
blue bold
Address Select Input 4:0.
When the LXT385 ransceiver is in the:
Data Transfer Acknowledge (Active Low) Output.
When the LXT385 ransceiver is in the Host Processor mode
using a Motorola processor, ACK acts as a data transfer
acknowledge. A low signal on ACK during a data bus operation
that is a:
NOTE: Wait states occur only if a write cycle immediately follows
For other pin functions, see RDY and SDO.
Address Latch Enable Input.
When the LXT385 ransceiver is in the:
For other pin functions, see AS and SCLK.
Address Strobe (Active Low) Input.
When the LXT385 ransceiver is in the:
For other pin functions, see ALE and SCLK.
• Host Processor mode using a parallel interface that is in the:
• Hardware mode, must be connected to ground. See
• Read operation indicates valid data.
• Write operation is an acknowledge signal that indicates a
• Host Processor mode using an Intel
• Hardware mode, ALE must be connected to ground.
• Host Processor mode using a Motorola processor in a
• Hardware mode, AS must be connected to ground.
• Non-multiplexed mode, A4:0 function as address pins.
• Multiplexed mode, A4:0 must be connected to multiplexed
5.7, “Signal Loss and Line-Code-Violation Signals”
pin functions.
data transfer into an addressed register is accepted.
interface, ALE acts as an address latch enable. In this case,
the address on the multiplexed address/data bus pins D7:0
(also called AD7:0) is clocked into the LXT385 ransceiver
with the falling edge of ALE.
parallel interface, AS acts as an active-low address strobe.
Signals”,
Address/Data Bus (AD).
a previous read or write cycle (for example, read-modify-
write).
print indicates the signal being discussed.
Table
Signal Description
12.
®
Revision Date: 19-Jan-2006
processor in a parallel
Document Number: 249252
Revision Number: 006
for other
Section