FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet
FWLXT9785BC.A4
Specifications of FWLXT9785BC.A4
Related parts for FWLXT9785BC.A4
FWLXT9785BC.A4 Summary of contents
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® The Intel LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/ Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction..................................................................................................................................17 1.1 What You Will Find in This Document ................................................................................ 17 1.2 Related Documents ............................................................................................................ 17 2.0 Block Diagram ............................................................................................................................. 18 3.0 Pin/Ball Assignments and Signal Descriptions ........................................................................ 19 3.1 PQFP Pin Assignments ...................................................................................................... 19 3.1.1 PQFP Pin ...
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Contents 4.3.7 MDIO Management Interface .............................................................................. 120 4.3.8 MII Sectionalization.............................................................................................. 122 4.3.9 MII Interrupts........................................................................................................ 122 4.3.10 Global Hardware Control Interface ...................................................................... 123 4.3.11 FIFO Initial Fill Values.......................................................................................... 123 4.4 Operating Requirements................................................................................................... 124 4.4.1 Power Requirements ........................................................................................... 124 4.4.2 Clock/SYNC Requirements ...
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... Link Failure ..........................................................................................150 4.10.4 Jabber ..................................................................................................................150 4.11 DTE Discovery Process .................................................................................................... 151 4.11.1 Definitions ............................................................................................................ 151 4.11.2 Interaction between Processor, MAC, and PHY ..................................................152 4.11.3 Management Interface and Control .....................................................................152 4.11.4 DTE Discovery Process Flow .............................................................................. 153 4.11.5 DTE Discovery Behavior...................................................................................... 154 4.12 Monitoring Operations ...
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... Power and Ground Supply Connections .................................................................................. 168 35 Typical Twisted-Pair Interface .................................................................................................. 169 ® 36 Recommended Intel LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry...... 170 ® 37 Recommended Intel LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ......... 171 38 ON Semiconductor Triple PECL-to-LVPECL Translator .......................................................... 172 6 Datasheet Document Number: 249241 Revision Number: 010 ...
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... RMII - 10BASE-T Transmit Timing ........................................................................................... 195 57 Auto-Negotiation and Fast Link Pulse Timing........................................................................... 196 58 Fast Link Pulse Timing .............................................................................................................196 59 MDIO Write Timing (MDIO Sourced by MAC) .......................................................................... 197 60 MDIO Read Timing (MDIO Sourced by PHY)........................................................................... 197 61 Power-Up Timing ...................................................................................................................... 198 62 RESET_L Recovery Timing ......................................................................................................198 63 PHY Identifier Bit Mapping........................................................................................................ 203 64 208-Pin PQFP Plastic Package Specification ...
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... Power Supply Signal Descriptions – BGA23 .............................................................................. 94 35 Unused/Reserved Pins – BGA23 ............................................................................................... 96 36 Receive FIFO Depth Configurations........................................................................................... 97 37 Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name ......................... 99 38 Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII) .... 103 ® ...
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... Register Set .............................................................................................................................. 199 83 Control Register (Address 0) .................................................................................................... 200 84 Status Register (Address 1)......................................................................................................201 85 PHY Identification Register 1 (Address 2) ................................................................................ 203 86 PHY Identification Register 2 (Address 3) ................................................................................ 203 87 Auto-Negotiation Advertisement Register (Address 4) ............................................................. 204 88 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ................................... 205 89 Auto-Negotiation Expansion Register (Address 6) ................................................................... 206 90 Auto-Negotiation Next Page Transmit Register (Address 7) .................................................... 206 91 Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ...
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... Modified Table 104 “Product Information” [added new packaging information]. Modified Figure 69 “Ordering Information - Sample” [changed Internal Package Designator for B 230 and E, and added the GD and definition under Intel Package Designator). Page Description All Globally added LEDn_3 to BGA15. ...
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... Assignments (Top View)”. Modified Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by 52 Signal Name”. Modified Table 19 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball 57 Location”. Modified Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by 62 Signal Name” ...
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... Added Section 4.13, “Cable Diagnostics Overview”. 161 Modified/added text under Section 4.13.3, “Implementation Considerations”. 162 Added Section 4.14, “Link Hold-Off Overview”. 173 Modified Table 52 “Intel 12 Revision Number: 007 Revision Date: August 28, 2003 (Sheet ® LXT9785/9785E Global Hardware Configuration Settings”. ...
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... Added table note to Table 66 “Intel 184 Parameters”. Added table note to Table 72 “Intel 190 Parameters” Added software power-down and note to Table 80 “Intel 198 Parameters”. 199 Modified paragraphs and added last paragraph under Section 7.0, “Register Definitions”. 199 Modified Table 82 “Intel 200 Modified Table 83 “ ...
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... Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph. 166 Replaced text under Section 5.2.5, “The Fiber Interface”. Replaced Figure 36 “Recommended Intel 170 Interface Circuitry”. Replaced Figure 37 “Recommended Intel 171 Circuitry”. 173 Modified Table 52 “Intel Modified Table 53 “Intel 174 V +/- 5%)” ...
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... Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced 70 Speed Mode” Modified Figure 38 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver 109 Interface Circuitry” Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface 110 Circuitry” 111 Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator” 112 Modified Table 28 “ ...
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... Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = 2. 126 Control Register table: Modified table and table notes. 128 PHY Identification Register 2 (Address 3): Modified table. 128 PHY Identifier Bit Mapping: Modified diagram. 131 Auto-Negotiation Expansion: Modified table and table notes. ...
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... LXT9785/LXT9785E Design and Layout Guide ® Intel LXT9785/LXT9785E Specification Update ® Intel LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/ LVPECL Interface IP Telephony and DTE Discovery Using Intel Ethernet Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 ® LXT9785 and LXT9785E Advanced 8-port ® ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 2.0 Block Diagram Figure 1 provides the LXT9785/LXT9785E block diagram. Figure 1. Block Diagram RMII/SMII Contr ADD_[4:0] MDIO 2 MDC 2 MDINT_L 2 TxDatan Counters Register Set Port LED Drivers 3 LEDn_[3:1]_L RxDatan 18 8-Port Global Functions Management / Mode Select Logic & ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.0 Pin/Ball Assignments and Signal Descriptions 3.1 PQFP Pin Assignments The following sections show PQFP pin assignments and signal descriptions: • Section 3.1.1, “PQFP Pin Assignments – RMII Configuration” on page 20 • ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.1.1 PQFP Pin Assignments – RMII Configuration Figure 2 and Table 2, “RMII PQFP Pin List” on page 21 pin assignments. Figure 2. RMII 208-Pin PQFP Assignments CRS_DV6 .....1 RxER6/LINKHOLD.....2 TxEN6 .....3 TxData6_0 .....4 TxData6_1 .....5 REFCLK1 .....6 RxData5_1 .....7 RxData5_0 .....8 GNDIO .....9 CRS_DV5 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 2. RMII PQFP Pin List Pin Symbol Type O, TS, 1 CRS_DV6 SL O, TS, RxER6/ 2 SL, ID, LINKHOLD TxEN6 TxData6_0 TxData6_1 REFCLK1 I O, TS, 7 RxData5_1 ID 8 RxData5_0 GNDIO – O, TS, 10 CRS_DV5 SL O, TS, RxER5 / 11 SL, ID, FIFOSEL1 I, ST ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type O, TS, RxER0/ 59 SL, ID, MDIX TxEN0 TxData0_0 TxData0_1 MDC0 I, ST, ID I/O, TS, 64 MDIO0 SL VCCD – 66 GNDD – OD, TS, 67 MDINT0_L SL, IP OD, TS, 68 LED3_3_L SO, IP OD, TS, 69 LED3_2_L SL, IP OD, TS, 70 LED3_1_L SL, IP OD, TS, ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type 125 TPFOP3 AO/AI 126 GNDR3 – 127 GNDT2/3 – 128 TPFIN3 AO/AI 129 TPFIP3 AO/AI 130 VCCR3 – 131 VCCR4 – 132 TPFIP4 AO/AI 133 TPFIN4 AO/AI 134 GNDT4/5 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type OD, TS, 194 LED7_3_L SL, IP 195 GNDD – 196 VCCD – O, TS, 197 RxData7_1 ID 198 RxData7_0 O, TS 199 GNDIO – O, TS, 200 CRS_DV7 SL O, TS, 201 RxER7 SL, ID 202 TxEN7 I, ID ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.1.2 PQFP Pin Assignments – SMII Configuration Figure 3 and Table 3, “SMII PQFP Pin List” on page 26 PQFP pin assignments. Figure 3. SMII 208-Pin PQFP Assignments NC ..... 1 NC/LINKHOLD ..... 2 NC ..... 3 TxData6 ..... 4 NC ..... 5 REFCLK1 ..... 6 NC ..... 7 RxData5 ..... 8 GNDIO ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 3. SMII PQFP Pin List Pin Symbol Type 1 NC NC/ 2 LINKHOLD TxData6 REFCLK1 RxData5 9 GNDIO FIFOSEL1 TxData5 RxData4 VCCIO 19 GNDIO 20 FIFOSEL0 TxData4 MDC1 I, ST, ID I/O, TS, 25 MDIO1 26 MDINT1_L TS, SL RxData3 29 VCCIO 30 GNDIO ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 68 LED3_3_L 69 LED3_2_L 70 LED3_1_L 71 LED2_3_L 72 LED2_2_L 73 LED2_1_L 74 GNDIO 75 LED1_3_L 76 LED1_2_L 77 LED1_1_L 78 VCCD 79 GNDD 80 LED0_3_L 81 LED0_2_L 82 LED0_1_L 83 AMDIX_EN 84 MDDIS 85 CFG_3 86 CFG_2 87 CFG_1 88 ADD_4 89 ADD_3 90 ADD_2 91 ADD_1 Datasheet Document Number: 249241 Revision Number: 010 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type 130 VCCR3 131 VCCR4 132 TPFIP4 133 TPFIN4 134 GNDT4/5 135 GNDR4 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 193 LED7_2_L 194 LED7_3_L 195 GNDD 196 VCCD 197 NC 198 RxData7 199 GNDIO 200 NC 201 NC 202 NC 203 TxData7 204 SYNC1 205 NC 206 RxData6 207 GNDIO 208 VCCIO Datasheet Document Number: 249241 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.1.3 PQFP Pin Assignments – SS-SMII Configuration Figure 4 and Table 4, “SS-SMII PQFP Pin List” on page 31 SMII PQFP pin assignments. Figure 4. SS-SMII 208-Pin PQFP Assignments NC ..... 1 NC/LINKHOLD ..... 2 NC ..... 3 TxData6 ..... 4 NC ..... 5 REFCLK1 ..... 6 RxData5 ..... 7 NC ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 4. SS-SMII PQFP Pin List Pin Symbol Type 1 NC NC/ 2 LINKHOLD TxData6 REFCLK1 7 RxData5 GNDIO FIFOSEL1 I, ID TxData5 RxData4 RxSYNC1 18 VCCIO 19 GNDIO 20 FIFOSEL0 I, ID RxCLK1 22 TxData4 MDC1 I, ST, ID I/O, TS, 25 MDIO1 OD, TS, ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type OD, TS, 67 MDINT0_L SL, IP OD, TS, 68 LED3_3_L SO, IP OD, TS, 69 LED3_2_L SL, IP OD, TS, 70 LED3_1_L SL, IP OD, TS, 71 LED2_3_L SL, IP OD, TS, 72 LED2_2_L SL, IP OD, TS, 73 LED2_1_L SL GNDIO OD, TS, 75 LED1_3_L SL, IP OD, TS, 76 LED1_2_L SL, IP OD, TS, 77 LED1_1_L ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type 135 GNDR4 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 TPFIP6 147 TPFIN6 148 GNDT6/7 149 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol Type 203 TxData7 204 TxSYNC1 O, TS, 205 RxData6 206 NC 207 GNDIO 208 VCCIO 34 Reference for Full 1 Description I, ID Table 6 (page 38 Table 8 (page 39) Table 8 (page 39) ID – Table 16 (page 49) – Table 15 (page 47) – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.2 PQFP Signal Descriptions 3.2.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are as follows: • Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 5. RMII Signal Descriptions – PQFP (Sheet Pin-Ball Designation PQFP PBGA 34 D8 A11, 23 C10 13 B13, 14 D11 4 D13, 5 A16 203 E14, 204 C16 60 E3, 51 B2, 41 C6, 33 A7, 21 B11, 12 A14, 3 C14, 202 D16 55 C2, ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 5. RMII Signal Descriptions – PQFP (Sheet Pin-Ball Designation PQFP PBGA 206 C15, 205 B17 198 E16, 197 F14 58 E4, 49 C4, 39 A5, 31 B8, 17 B12, 10 D12, 1 B16, 200 E15 59 D2, 50 D5, 40 D7, 32 C8, ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 6. SMII/SS-SMII Common Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 61 E2, 52 C3, 42 B5, 34 D8, 22 A11, 13 B13, 4 D13, 203 E14 E6, 44 REFCLK0 6 REFCLK1 E12 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 8. SS-SMII Specific Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 35 A6, 204 C16 58 E4, 17 B12 32 C8, 201 D17 60 E3, 21 B11 54 B1, 45 B4, 36 C7, 27 B9, 15 C12, 7 B15, 205 B17, 197 F14 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... Symbol Type Signal Description Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 I/O, TS, SL, MDIO0 is used when 1x8 port sectionalization is MDIO1 IP selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7. ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 10. Signal Detect – PQFP Pin/Ball Designation PQFP PBGA P2, 97 N4, 100 P3, 101 N5, 161 P15, 162 P16, 165 P17, 166 N17 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 12. JTAG Test Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 167 N14 168 N15 169 N16 170 M16 171 M17 1. Type Column Coding Input Output Open Drain Three-State-able output, SMT = Schmitt Triggered input Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... Reset Register bit 0.15. When held Low, all outputs are forced to inactive state. Pin is not on JTAG chain. Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. ADD_4 Port 0 Address = Base ADD_3 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 13. Miscellaneous Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA L2 173 M14 1. Type Column Coding Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 13. Miscellaneous Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 11 A15 20 A12 A17 1. Type Column Coding Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 14. LED Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 82 K3 J4 H2 F2 180 K16, 181 K17, 182 J17 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 14. LED Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 185 J15, 186 J16, 187 H17 189 H15, 190 H16, 191 G17 192 G15, 193 F17, 194 F16 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 15. Power Supply Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 103, 116, N13, P4, 117, 130, P7, P8, 131, 144, P9, P10, 145, 158 P11, P12 N6, N7, 109, 123, N9, N11, 138, 152 N12 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 16. Unused/Reserved Pins – PQFP Pin/Ball Designation PQFP PBGA F15, G2, G5, G14, G16, H4, NC H14, J2, J13, K4, K15 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3 BGA23 Ball Assignments The following sections provide BGA23 ball location and signal description information for RMII, SMII, and SS-SMII: • Table 3.3.1 “RMII BGA23 Ball List” on page 51 • Table 3.3.2 “SMII BGA23 Ball List” on page 61 • ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.1 RMII BGA23 Ball List The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: • Table 18 “RMII BGA23 Ball List in Alphanumeric Order by Signal Name” ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDT P14 – GNDT R1 – GNDT R3 – GNDT R5 – GNDT R15 – GNDT R17 – GNDT T17 – GNDT U2 – GNDT U4 – GNDT U6 – GNDT U10 – GNDT U12 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type No ball F6 – No ball F7 – No ball F8 – No Ball E8 – No Ball E10 No Ball F9 – No Ball F10 – No Ball F11 – No Ball F12 – No Ball G6 – No Ball G7 – No Ball G8 – No Ball G9 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type RxER5 O, TS, SL, A15 (FIFOSEL1) ID RxER6 O, TS, SL, A17 LINKHOLD I, ID TS, SL, RxER7 D17 ID SD_2P5V P1 I, ST, ID SD0 P2 I SD1 N4 I SD2 P3 I SD3 N5 I SD4 P15 I SD5 P16 I SD6 P17 I ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type TxEN7 D16 I, ID TxSLEW_0 N3 I, ST, ID TxSLEW_1 M4 I, ST, ID VCCD F5 – VCCD G13 – VCCD J5 – VCCD J14 – VCCIO A2 – VCCIO A8 – VCCIO C1 – VCCIO C11 – VCCIO D14 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 19. RMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Signal Type A1 GNDD – A2 VCCIO – A3 RxData1_0 TxData2_1 TS, SL, A5 CRS_DV2 ID A6 TxData3_1 TxEN3 VCCIO – A9 GNDD – I/O, TS, A10 MDIO1 SL, IP A11 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type D14 VCCIO – D15 GNDD – D16 TxEN7 TS, SL, D17 RxER7 ID E1 MDC0 I, ST TxData0_0 TxEN0 TS, SL, E4 CRS_DV0 ID E5 GNDD – E6 REFCLK0 I E7 GNDD – Ball – E9 GNDD – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type H12 No Ball – H13 No Ball – H14 NC – OD, TS, H15 LED6_1_L SL, IP OD, TS, H16 LED6_2_L SL, IP OD, TS, H17 LED5_3_L SL, IP OD, TS, J1 LED0_3_L SL – OD, TS, J3 LED1_2_L SL, IP OD, TS, J4 LED1_1_L SL, IP ...
Page 59
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type M12 No Ball – M13 GNDPECL – M14 G_FX/TP_L I, ST, ID M15 RESET_L I, ST, IP M16 TCK I, ST, ID M17 TRST_L I, ST ADD_1 I, ST ADD_0 I, ST TxSLEW_0 I, ST SD1 I N5 SD3 I N6 VCCT – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type U3 TPFIP1 AO/AI U4 GNDT – U5 TPFON2 AO/AI U6 GNDT – U7 TPFOP3 AO/AI U8 GNDR – U9 TPFIN4 AO/AI U10 GNDT – U11 TPFON5 AO/AI U12 GNDT – U13 TPFIP5 AO/AI U14 GNDT – ...
Page 61
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.2 SMII BGA23 Ball List The following tables provide the SMII ball locations and signal names arranged in alphanumeric order as follows: • Table 20 “SMII BGA23 Ball List in Alphanumeric Order by Signal Name” • ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDT U6 – GNDT U10 – GNDT U12 – GNDT U14 – GNDT U16 – GNDT U17 – OD, TS, LED0_1_L K3 SL, IP OD, TS, LED0_2_L K2 SL, IP OD, TS, LED0_3_L J1 SL, IP OD, TS, LED1_1_L J4 SL, IP ...
Page 63
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type NC C10 – NC C12 – NC C14 – – NC D11 – NC D12 – NC D16 – NC D17 – – – NC E15 – – NC F14 – NC F15 – – – NC G14 – NC G16 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type PREASEL D7 I, ID, ST PWRDWN L14 I, ID, ST REFCLK0 E6 I REFCLK1 E12 I RESET_L M15 I, ST, IP RxData0 C2 O, TS, ID RxData1 A3 O, TS, ID RxData2 B6 O, TS, ID RxData3 D9 O, TS, ID RxData4 A13 O, TS, ID RxData5 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type VCCD J14 – VCCIO A2 – VCCIO A8 – VCCIO C1 – VCCIO C11 – VCCIO D14 – VCCPECL L5 – VCCPECL L13 – VCCR N13 – VCCR P4 – VCCR P7 – VCCR P8 – ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 21. SMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Signal Type A1 GNDD – A2 VCCIO – A3 RxData1 O, TS – – A6 SYNC0 – A8 VCCIO – A9 GNDD – I/O, TS, A10 MDIO1 SL, IP A11 TxData4 ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type E2 TxData0 – – E5 GNDD – E6 REFCLK0 I E7 GNDD – Ball – E9 GNDD – E10 No Ball E11 GNDD – E12 REFCLK1 I E13 GNDD – E14 TxData7 I, ID E15 NC – E16 RxData7 ...
Page 68
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type OD, TS, H17 LED5_3_L SL, IP OD, TS, J1 LED0_3_L SL – OD, TS, J3 LED1_2_L SL, IP OD, TS, J4 LED1_1_L SL VCCD – Ball – Ball – J8 GNDD – J9 GNDD – J10 GNDD – J11 No Ball – J12 No Ball – ...
Page 69
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type N2 ADD_0 I, ST TxSLEW_0 I, ST SD1 I N5 SD3 I N6 VCCT – N7 VCCT – Ball – N9 VCCT – N10 No Ball – N11 VCCT – N12 VCCT – N13 VCCR – N14 TDI ...
Page 70
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type U10 GNDT – U11 TPFON5 AO/AI U12 GNDT – U13 TPFIP5 AO/AI U14 GNDT – U15 TPFON6 AO/AI U16 GNDT – U17 GNDT – Datasheet Document Number: 249241 Revision Number: 010 ...
Page 71
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.3 SS-SMII BGA23 Ball List The following tables provide the SS-SMII ball locations and signal names arranged in alphanumeric order as follows: • Table 22 “SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name” • ...
Page 72
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDT U10 – GNDT U12 – GNDT U14 – GNDT U16 – GNDT U17 – OD, TS, LED0_1_L K3 SL, IP OD, TS, LED0_2_L K2 SL, IP OD, TS, LED0_3_L J1 SL, IP OD, TS, LED1_1_L J4 SL, IP OD, TS, ...
Page 73
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type NC D9 – NC D11 – NC D12 – NC D16 – NC E15 – NC E16 – – NC F15 – – – NC G14 – NC G16 – – NC H14 – – NC J13 – – NC K15 – ...
Page 74
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type RxData0 B1 O, TS, ID RxData1 B4 O, TS, ID RxData2 C7 O, TS, ID RxData3 B9 O, TS, ID RxData4 C12 O, TS, ID RxData5 B15 O, TS, ID RxData6 B17 O, TS, ID RxData7 F14 O, TS, ID RxSYNC0 E4 O, TS, ID RxSYNC1 B12 O, TS, ID ...
Page 75
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type VCCIO A2 – VCCIO A8 – VCCIO C1 – VCCIO C11 – VCCIO D14 – VCCPECL L5 – VCCPECL L13 – VCCR N13 – VCCR P4 – VCCR P7 – VCCR P8 – VCCR P9 – VCCR P10 – ...
Page 76
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 23. SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Signal Type A1 GNDD – A2 VCCIO – – – – A6 TxSYNC0 – A8 VCCIO – A9 GNDD – I/O, TS, A10 MDIO1 SL, IP A11 TxData4 I, ID ...
Page 77
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type E4 RxSYNC0 O, TS GNDD – E6 REFCLK0 I E7 GNDD – Ball – E9 GNDD – E10 No Ball – E11 GNDD – E12 REFCLK1 I E13 GNDD – E14 TxData7 I, ID E15 NC – E16 NC – ...
Page 78
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type J2 NC – OD, TS, J3 LED1_2_L SL, IP OD, TS, J4 LED1_1_L SL VCCD – Ball – Ball – J8 GNDD – J9 GNDD – J10 GNDD – J11 No Ball J12 No Ball – J13 NC – J14 VCCD – ...
Page 79
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type N5 SD3 I N6 VCCT – N7 VCCT – Ball – N9 VCCT – N10 No Ball – N11 VCCT – N12 VCCT – N13 VCCR – N14 TDI I, ST, IP N15 TDO O, TS N16 TMS ...
Page 80
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type U13 TPFIP5 AO/AI U14 GNDT – U15 TPFON6 AO/AI U16 GNDT – U17 GNDT – Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Reference for 1 Full Description ...
Page 81
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.4 BGA23 Signal Descriptions 3.4.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are as follows: • Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation ...
Page 82
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 24. RMII Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP D8 A11, 22 C10 23 B13, 13 D11 14 D13, 4 A16 5 E14, 203 C16 204 E3, 60 B2, 51 C6, 41 A7, 33 B11, 21 A14, 12 C14, 3 D16 202 C2 A3 B6, ...
Page 83
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 24. RMII Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP C15, 206 B17 205 E16, 198 F14 197 E4, 58 C4, 49 A5, 39 B8, 31 B12, 17 D12, 10 B16, 1 E15 200 D2, 59 D5, 50 D7, 40 C8, ...
Page 84
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 25. SMII/SS-SMII Common Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP E2, 61 C3, 52 B5, 42 D8, 34 A11, 22 B13, 13 D13, 4 E14 203 E6 E12 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 85
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 27. SS-SMII Specific Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP A6, 35 C16 204 E4, 58 B12 17 C8, 32 D17 201 E3, 60 B11 21 B1, 54 B4, 45 C7, 36 B9, 27 C12, 15 B15, 7 B17, 205 F14 197 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 86
... Revision Date: 30-May-2006 1 Symbol Type Signal Description Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 I/O, TS, SL, MDIO0 is used when 1x8 port sectionalization is MDIO1 IP selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7. ...
Page 87
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 29. Signal Detect – BGA23 Ball/Pin Designation BGA23 PQFP P1 95 P2, 96 N4, 97 P3, 100 N5, 101 P15, 161 P16, 162 P17, 165 N17 166 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 88
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 31. JTAG Test Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP N14 167 N15 168 N16 169 M16 170 M17 171 1. Type Column Coding Input Output Open Drain Three-State-able output, SMT = Schmitt Triggered input Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 89
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP N3 L14 174 M15 175 1. Type Column Coding Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down ...
Page 90
... Revision Number: 010 Revision Date: 30-May-2006 1 Symbol Type Signal Description Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. ADD_4 Port 0 Address = Base ADD_3 Port 1 Address = Base + 1 ADD_2 I, ST, ID Port 2 Address = Base + 2 ...
Page 91
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP D2 59 L2 M14 173 1. Type Column Coding Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down ...
Page 92
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP A15 11 A12 A17 2 1. Type Column Coding Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down ...
Page 93
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 33. LED Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP K3 J4 H2 F2 K16, 180 K17, 181 J17 182 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 94
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 33. LED Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP J15, 185 J16, 186 H17 187 H15, 189 H16, 190 G17 191 G15, 192 F17, 193 F16 194 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 95
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 34. Power Supply Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP N13, P4, 103, 116, P7, P8, 117, 130, P9, P10, 131, 144, P11, P12 145, 158 N6, N7, 109, 123, N9, N11, 138, 152 N12 ...
Page 96
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 35. Unused/Reserved Pins – BGA23 Pin/Ball Designation BGA23 PQFP RMII - No Connection F15, G2, G5, G14, G16, H4, NC H14, J2, J13, K4, K15 SMII - No Connection A4, A5, A7, A14, A16, B1, B2, B4, B8, B9, B11, B12, B15, B16, B17, C4, ...
Page 97
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 36. Receive FIFO Depth Configurations FIFOSEL1 Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 FIFOSEL0 Register 18.15 Value Register 18.14 Value ...
Page 98
... Figure 6 “196-Ball BGA15 Assignments (Top View)” • Table 37, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” on page 99 • Table 38, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII)” on page 103 Figure 6. 196-Ball BGA15 Assignments (Top View ...
Page 99
... The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: Table 37 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” Table 38 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII)” Table 37. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name ...
Page 100
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Name GNDD J6 GNDD J7 GNDD J8 GNDD K5 GNDD K6 GNDD K9 GNDD K10 GNDD L2 GNDD N1 GNDD N11 GNDD P1 GNDD P11 LED0_1_L N9 LED0_2_L P9 LED0_3_L M8 LED1_1_L N8 LED1_2_L P8 LED1_3_L L8 LED2_1_L P7 LED2_2_L N7 LED2_3_L M7 LED3_1_L P6 LED3_2_L N6 LED3_3_L M6 100 Reference for Full ...
Page 101
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Name D10 L10 REFCLK0 L4 REFCLK1 C3 RESET_L C10 O, TS, RXCLK G1 RxData0_S N3 O, TS, RxData0_SS M3 RxData1_S M2 O, TS, RxData1_SS M1 RxData2_S K2 O, TS, RxData2_SS J2 RxData3_S H3 O, TS, RxData3_SS H2 RxData4_S F2 O, TS, RxData4_SS F3 RxData5_S E3 RxData5_SS C2 Datasheet Document Number: 249241 ...
Page 102
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Name TPON7 B13 TPOP0 P13 TPOP1 N14 TPOP2 K13 TPOP3 J14 TPOP4 F14 TPOP5 E13 TPOP6 B14 TPOP7 A13 TRST_L A10 TXCLK J3 TxData0 N4 TxData1 N2 TxData2 K3 TxData3 J1 TxData4 G3 TxData5 E2 TxData6 D3 TxData7 ...
Page 103
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 38 shows the ball locations and signal names arranged in order by ball location. Table 38. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII) Ball Signal Name A1 GNDD A2 GNDD A3 GNDD A4 RxData6_SS ...
Page 104
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name C13 TPIN6 C14 TPIP6 TxData6 D4 VCCIO D5 LED7_3_L D6 LED6_3_L D7 VCCD D8 LED4_3_L D9 GNDD D10 NC D11 GNDD D12 AVCC D13 TPIP5 D14 TPIN5 E1 RxSYNC E2 TxData5 E3 RxData5_S GNDD E6 GNDD 104 Reference for Full ...
Page 105
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name G3 TxData4 G4 GNDD GNDD G7 GNDD G8 GNDD G9 AVSS G10 AVSS G11 AVSS G12 AVCC G13 TPIN4 G14 TPIP4 RxData3_SS H3 RxData3_S H4 VCCIO GNDD H7 GNDD H8 GNDD H9 AVSS H10 AVSS H11 AVSS H12 AVCC ...
Page 106
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name K9 GNDD K10 GNDD K11 AVSS K12 AVCC K13 TPOP2 K14 TPON2 GNDD L3 VCCIO L4 REFCLK0 L5 VCCIO VCCD L8 LED1_3_L L9 CFG_2 L10 NC L11 AVSS L12 AVCC L13 TPIP2 L14 TPIN2 M1 RxData1_SS M2 RxData1_S ...
Page 107
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name N11 GNDD N12 TPIN0 N13 TPON0 N14 TPOP1 P1 GNDD MDC P5 MDINT_L P6 LED3_1_L P7 LED2_1_L P8 LED1_2_L P9 LED0_2_L P10 ADD_3 P11 GNDD P12 TPIP0 P13 TPOP0 P14 TPON1 Datasheet Document Number: 249241 ...
Page 108
... For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1. 3.6.2 Signal Descriptions – SMII and SS-SMII Configurations Table 39 provides the BGA15 signal descriptions. ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol TxData0 TxData1 TxData2 TxData3 TxData4 ...
Page 109
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol RxData0_S RxData1_S RxData2_S RxData3_S RxData4_S RxData5_S RxData6_S RxData7_S TxSYNC RxSYNC TxCLK RxCLK RxData0_SS RxData1_SS RxData2_SS RxData3_SS RxData4_SS RxData5_SS RxData6_SS RxData7_SS MDIO MDINT_L 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 110
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol MDC TPOP0, TPON0 TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 TPOP4, TPON4 TPOP5, TPON5 TPOP6, TPON6 TPOP7, TPON7 TPIP0, TPIN0 TPIP1, TPIN1 TPIP2, TPIN2 ...
Page 111
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol TxSLEW_0 TxSLEW_1 RESET_L ADD_4 ADD_3 MODESEL_1 MODESEL_0 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 112
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol AMDIX_EN CFG_1 CFG_2 CFG_3 FIFOSEL1 FIFOSEL0 LINKHOLD LED0_1_L LED0_2_L LED0_3_L 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 113
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol LED1_1_L LED1_2_L LED1_3_L LED2_1_L LED2_2_L LED2_3_L LED3_1_L LED3_2_L LED3_3_L LED4_1_L LED4_2_L LED4_3_L LED5_1_L LED5_2_L LED5_3_L LED6_1_L LED6_2_L LED6_3_L LED7_1_L LED7_2_L LED7_3_L AVCC 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 114
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet Symbol F11, G9, G10, AVSS G11, H9, H10, VCCD VCCIO B10, D9, D11, GNDD J5, J6, J7, J8, SGND NC 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down ...
Page 115
... Note: Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E. 4.1.1 OSP™ Architecture The Intel LXT9785/LXT9785E incorporates high-efficiency Optimal Signal Processing™ design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. ...
Page 116
... LXT9785/LXT9785E auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. ...
Page 117
... The LXT9785/LXT9785E supports either 100BASE-TX or 10BASE-T connections over 100 Ω, Category 5, Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are required to complete this interface. Using Intel's patented waveshaping technology, the transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 13, “ ...
Page 118
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.2.1.2 MDI Crossover (MDIX) The LXT9785/LXT9785E crossover function, which is compliant to the IEEE 802.3, clause 23 standard, connects the transmit output of the device to the far-end receiver in a link segment. This function can be disabled via Register bits 27.9 using the hardware configuration pins. ...
Page 119
... Internal Loopback Register bit 0.14 must be set to enable internal loopback operation. Register bits 16.14 and 0.8 must be set for 10 Mbps operation. Intel recommends that auto-negotiation be disabled while internal loopback is enabled. The normal auto-negotiation process code word exchange cannot be completed.The following two-step sequence is recommended for the most efficient mode change when enabling forced 100 Mbps internal loopback mode directly from auto-negotiation mode: 1 ...
Page 120
... TxCLK, TxSYNC, RxCLK, and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the MAC and in reference to the REFCLK. ...
Page 121
... X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are completely disabled ...
Page 122
... MII Sectionalization When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function is unaffected and operates normally. Sectionalization is selected by pulling pin 176 (Section) High ...
Page 123
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers • Auto-negotiation complete. • Speed status change. • Duplex status change. • Link status change. • Isolate status change. Figure 12. Interrupt Logic Event X Enable Reg Event X Status Reg . . . Per Event Force Interrupt Int errupt (Event) Status Register is cleared on read ...
Page 124
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.4 Operating Requirements 4.4.1 Power Requirements The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground ...
Page 125
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.4.2.5 RxCLK Signal (SS-SMII Only) In SS-SMII mode, the LXT9785/LXT9785E provides a 125 MHz clock output in reference to the output RxDatan. RxCLK is referenced and synchronized to the REFCLK. See 140. Note: Although RXCLK is referenced to REFCLK, the RXCLK may vary in cumulative phase four bit-times relative to REFCLK ...
Page 126
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 13. Initialization Sequence Pass Control to MDIO Reset MDIO Registers to Control Interface at last 4.5.3 Power-Down Mode The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible. The device can be put into a low-power state via Register 0 as well as a near-zero power state with the power down pin ...
Page 127
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Note: Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware power-down or link hold-off modes. The recovery times are specified in “Power-Up Timing Parameters” on page 198 4.5.3.1 Global (Hardware) Power Down The global power-down mode is controlled by the PWRDWN pin ...
Page 128
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware reset. The recovery times are specified in page 198 4.5.5 Hardware Configuration Settings The LXT9785/LXT9785E provides a hardware option to set the initial device configuration. The hardware option uses three Global CFG pins that provide control for all ports (see Table 42 ...
Page 129
... Mbps link can come period of transmit and receive idle time. TXEN and RXDV are inactive at the same time. This ensures that link is not brought up in the middle of transmitting or receiving a packet. To ensure link establishment, Intel recommends no packet transmission into the MII interface until link is established. ...
Page 130
... The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions: • Conveys complete MII information between a 10/100 PHY and MAC with two pins per port. • Allows a multi-port MAC/PHY communication with one system clock. ...
Page 131
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers • Supports per-packet switching between 10 Mbps and 100 Mbps data rates. The Serial MII operates at 125 MHz using a global reference clock and frame synchronization signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and RxDatan) ...
Page 132
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 15. Typical SMII Interface 125 MHz Sourced Externally or from Switch ASIC 132 Typical SMII Interface in a 16-Port System SECTION 8 TxDatan SYNC0 8 RxDatan MDIO0 MDC0 MDINT0 RefCLK0 RefCLK1 SYSTEM CLK RefCLK0 RefCLK1 8 TxDatan ...
Page 133
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 16. Typical SMII Quad Sectionalization 125 MHz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Typical SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxDatan SYNC0 ...
Page 134
... 4.7.1 SMII Reference Clock The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always be synchronized to the REFCLK by the MAC and PHY. The LXT9785/LXT9785E samples these signals on the rising edge of the REFCLK. 4.7.2 TxSYNC Pulse (SMII/SS-SMII) The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must continuously generate a TxSYNC pulse once every 10 REFCLK cycles ...
Page 135
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 18. Serial MII Transmit Synchronization CLOCK TxSYNC TX TxER TxEN 4.7.4 Receive Data Stream Receive data and control information are signalled in ten-bit segments. In 100 Mbps mode, each segment contains a new byte of data Mbps mode, each segment is repeated ten times (except for the CRS bit), and the MAC can sample any of the ten segments ...
Page 136
... Source Synchronous-Serial Media Independent Interface Some system designs require the PHY to be placed between inches away from the MAC. A new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added because of this requirement. To provide a source synchronous interface between the PHY and MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC ...
Page 137
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 45. SS-SMII Signal To TxData PHY TxCLK PHY TxSYNC PHY RxData MAC RxCLK MAC RxSYNC MAC REFCLK MAC Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 From Purpose MAC Transmit data & control ...
Page 138
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 20. Typical SS-SMII Interface 125 MHz Sourced Externally or from Switch ASIC 138 Typical SS-SMII Interface in a 16-Port System SECTION 8 TxData n TxSYNC0 TxCLK0 8 RxDatan RxSYNC1 RxCLK1 MDIO0 MDC0 MDINT0 RefCLK0,1 SYS_CLK RefCLK0,1 8 TxDatan ...
Page 139
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 21. Typical SS-SMII Quad Sectionalization 125 MHz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Typical SS-SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxData n TxSYNC0 ...
Page 140
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 22. SS-SMII Transmit Timing TxCLK TxSYNC TxData TxCLK TxSYNC TxData All signals are synchronous to the clock Figure 23. SS-SMII Receive Timing RxCLK RxData 4.8 RMII Operation The LXT9785/LXT9785E provides an independent Reduced MII port for each network port. Each RMII uses four signals to pass received data to the MAC: RxDatan< ...
Page 141
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.8.2 Transmit Enable TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted after the last bit of the packet. ...
Page 142
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 25. Typical RMII Interface 50 Mhz Sourced Externally or from Switch ASIC 142 Typical RMII Interface in a 16-Port System SECTION 8 TxD0n 8 TxD1n 8 TxENn 8 RxD0n 8 RxD1n 8 CRS_DVn 8 RxERn MDIO0 MDC0 MDINT0 RefClk0 RefClk1 RefClk0 RefClk1 ...
Page 143
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 26. Typical RMII Quad Sectionalization 50 MHz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Typical RMII Interface in a 24-Port System RefClk0 RefClk1 8 TxD0n 8 TxD1n 8 TxENn ...
Page 144
... PCS Sublayer The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function ...
Page 145
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.2.1.1 Preamble Handling When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of- Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer continues to encode the remaining RMII data until TxEN is de-asserted (see Table 46 on page 146) ...
Page 146
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3 PMA Sublayer The 100BASE-X PMA protocol uses the 4B/5B data encoding scheme to encode/decode the data streams. The coding scheme is shown in Table 46. 4B/5B Coding 4B Code Code Type DATA IDLE undefined CONTROL undefined ...
Page 147
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3.1 Link In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses lock (<16 consecutive idle symbols during window), the link is taken down. This provides a robust link, filtering out any small noise hits that may otherwise disrupt the link ...
Page 148
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3.6 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. ...
Page 149
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers The far-end fault detection process in fiber operation requires idles to establish link. Link will not establish if a far-end fault pattern is the initial signal detected. Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link Pass is selected (16 ...
Page 150
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.10.2 Dribble Bits The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the RMII. If five through seven dribble bits are received, the second nibble is not sent onto the RMII bus. ...
Page 151
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.11 DTE Discovery Process The DTE discovery process is port dependent and must be enabled through software. The process is implemented as a next page option to the auto-negotiation flow. When the process is enabled, manual control of auto-negotiation next pages is not allowed. This feature applies to the LXT9785E transceiver only ...
Page 152
... The processor communicates with the power supply unit (PSU) and switches it on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the MAC using the MDIO interface. The required control bits are contained in the PHY device register ...
Page 153
... FLP bursts, the status of the next page ability bit is checked. If the detected “link partner” also supports next page, then the LXT9785E transmits out the next page sequence Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Figure 30, “Intel® LXT9785E for a flow chart of the discovery process.When DTE 204). 153 ...
Page 154
... These values are loaded with randomly created data from an internal LSFR that is free running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in The receiver monitors the next pages to determine that the exact next page data (especially the random data) transmitted is received ...
Page 155
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers process. If each page is successfully auto-negotiated (it matches the transmitted page), DTE Discovery completes as previously described. The five Next Pages consist of a message page and four user pages. ® Figure 30. Intel LXT9785E Negotiation Flow Chart LFIT Expired 27 Dis_EN 27 FLP Detected Link Down 1 ...
Page 156
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.12 Monitoring Operations 4.12.1 Monitoring Auto-Negotiation Auto-negotiation may be monitored as follows: • Bits 1.2 and 17. once the link is established. • Additional bits in Register 1 (refer to Register 17 (refer to be used to determine the link operating conditions and status. ...
Page 157
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers When a long event (such as duplex status) occurs edge detected and starts the stretch timer. When the stretch timer expires, the edge detector is reset so that a long event causes another pulse to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED driver to remain asserted ...
Page 158
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers The LXT9785/LXT9785E includes an IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. 4.12.4 Boundary Scan Interface This interface consists of five pins (TMS, TDI, TDO, TCK and TRST_L). It includes a state machine, data register array, and instruction register ...
Page 159
... Cable Diagnostic tests report the distance to a cable fault based on the velocity of signal propagation, which is used to determine the electrical length to the fault. The electrical length may vary slightly from the physical cable length. The measurement accuracy may vary by +/- 2 m. The following basic equation is used to calculate the distance to a fault: Distance_to_Fault = (Reg29[7: ...
Page 160
... Cable Diagnostic pulse. Auto MDI/MDIX on the link partner should be accounted for in deriving the cable testing algorithm. Intel recommends auto MDI/MDIX be disabled when running the cable tests. The transmit and receive twisted-pairs must be tested one at a time with both short and long cable test suites. The MDI/MDIX control bits in can be used to select the twisted-pair to be tested ...
Page 161
... Link Hold-Off, once enabled by hardware configuration, is re- enabled on a port by issuing a software reset for that port not necessary to reset the entire PHY or switch system to re-enable Link Hold-Off. ...
Page 162
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or clearing Register bit 0.11, the power-down bit, during normal operation not required to have previously enabled Link Hold-Off by hardware configuration. Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the MDIO interface required to re-enable normal transmit and receive link operation ...
Page 163
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Method One: This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last power hardware reset. 1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port. 2. Program the PHY to the desired configuration. ...
Page 164
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 5.0 Application Information 5.1 Design Recommendations The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT9785/LXT9785E, attention to detail and good design practices are required ...
Page 165
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785/LXT9785E, helping with line performance. Second, if the VCC planes are laid out correctly, digital switching noise is kept away from external connectors, reducing EMI problems ...
Page 166
... Both 3.3 V fiber transceivers and 5 V fiber transceivers can be used with the LXT9785/ LXT9785E. See the 100BASE-FX Fiber Optic Transceivers-Connecting a PECL/LVPECL Interface Application Note (document number 250781) for detailed information on fiber interface designs and recommendations for Intel PHYs. The following should occur in 3.3 V fiber transceiver applications as shown in • ...
Page 167
... The following occurs fiber transceiver applications as shown in • The transmit pair should be AC-coupled and re-biased PECL input levels • The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to- fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note) • ...
Page 168
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 5.3 Typical Application Circuits Figure 34 through Figure 37 on page 171 LXT9785E. Figure 38 on page 172 Figure 34. Power and Ground Supply Connections GNDR/GNDT VCCR/VCCT LXT9785/9785E VCCIO VCCPECL GNDPECL 168 show typical application circuits for the LXT9785/ shows the interface circuitry for the logic translator ...
Page 169
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 35. Typical Twisted-Pair Interface LXT9785/9785E 1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT9785/ LXT9785E. 2. The 100 Ω receive load termination resistor typically required is integrated in the LXT9785/ Datasheet Document Number: 249241 ...
Page 170
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 36. Recommended Intel Circuitry +2.5V TPFONn TPFOPn LXT9785(E) SDn TPFINn TPFIPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 170 ® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface +3.3V +2.5V 0.01μ F 0.01μ ...
Page 171
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 37. Recommended Intel Circuitry TPFONn TPFOPn LXT9785(E) SDn TPFINn TPFIPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 2. See Figure 38 on page 172 Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 ® ...
Page 172
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 38. ON Semiconductor Triple PECL-to-LVPECL Translator 0.01 μF 5V 82Ω PECL Input Signal (5V Fiber Txcvr) 130Ω 172 5V 3.3V ON Semiconductor* Vcc Vcc VBB PECL 4 17 LVCC VBB PECL 7 14 LVCC GND Vcc ...
Page 173
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 6.0 Test Specifications Note: Table 51 through Table 81 the LXT9785/LXT9785E. These specifications are not guaranteed and are subject to change without notice. Minimum and maximum values listed in recommended operating conditions specified in Table 51. Absolute Maximum Ratings ...
Page 174
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 52. Operating Conditions (Sheet Parameter 100BASE-TX 100BASE-FX Operating 10BASE-T 3 Current - SMII Power-Down Hardware Auto-Negotiation 100BASE-TX 100BASE-FX Operating 10BASE-T Current - 3 SS-SMII Power-Down Hardware Auto-Negotiation 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing ...
Page 175
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 54. Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) Parameter Input Low voltage Input High voltage Input current Output Low voltage Output Low voltage (LED pins) Output High voltage 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 55. Digital I/O DC Electrical Characteristics – ...
Page 176
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 57. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Jitter magnitude (measured differentially) 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω ...
Page 177
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 59. 10BASE-T Transceiver Characteristics Parameter Peak differential output voltage Link transmit period Jitter magnitude added by the MAU and PLS sections Receive input impedance Link min receive timer Link max receive timer Differential squelch threshold 1. Typical values are at 25 ° ...
Page 178
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 39. SMII - 100BASE-TX Receive Timing REFCLK SYNC RxData TPFI Table 60. SMII - 100BASE-TX Receive Timing Parameters Parameter RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de- ...
Page 179
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 40. SMII - 100BASE-TX Transmit Timing REFCLK SYNC TxData TPFO Table 61. SMII - 100BASE-TX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold from REFCLK rising edge and ...
Page 180
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 41. SMII - 100BASE-FX Receive Timing REFCLK SYNC RxData TPFI Table 62. SMII - 100BASE-FX Receive Timing Parameters Parameter RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de- ...
Page 181
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 42. SMII - 100BASE-FX Transmit Timing REFCLK SYNC TxData TPFO Table 63. SMII - 100BASE-FX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold from REFCLK rising edge ...
Page 182
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 43. SMII - 10BASE-T Receive Timing REFCLK SYNC RxData TPFI Table 64. SMII - 10BASE-T Receive Timing Parameters Parameter RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive Start-of-Frame to CRS asserted Receive Start-of-Idle to CRS ...
Page 183
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 44. SMII - 10BASE-T Transmit Timing REFCLK SYNC TxData TPFO Table 65. SMII-10BASE-T Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold to REFCLK rising edge and ...
Page 184
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 45. SS-SMII - 100BASE-TX Receive Timing REFCLK RxCLK RxSYNC RxData TPFI Table 66. SS-SMII - 100BASE-TX Receive Timing Parameters Parameter REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time ...
Page 185
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 46. SS-SMII - 100BASE-TX Transmit Timing TxCLK TxSYNC TxData TPFO Table 67. SS-SMII - 100BASE-TX Transmit Timing Parameter TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold from TxCLK rising edge and ...
Page 186
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 47. SS-SMII - 100BASE-FX Receive Timing REFCLK RxCLK RxSYNC RxData TPFI Table 68. SS-SMII - 100BASE-FX Receive Timing Parameters Parameter REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time ...
Page 187
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 48. SS-SMII - 100BASE-FX Transmit Timing TxCLK TxSYNC TxData TPFO Table 69. SS-SMII - 100BASE-FX Transmit Timing Parameters Parameter TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold from TxCLK rising edge and ...
Page 188
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 49. SS-SMII - 10BASE-T Receive Timing REFCLK RxCLK RxSYNC RxData TPFI Table 70. SS-SMII - 10BASE-T Receive Timing Parameters Parameter REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time ...
Page 189
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 50. SS-SMII - 10BASE-T Transmit Timing TxCLK TxSYNC TxData TPFO Table 71. SS-SMII - 10BASE-T Transmit Timing Parameters Parameter TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold to TxCLK rising edge and TxData ...
Page 190
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 51. RMII - 100BASE-TX Receive Timing REFCLK RxData[1:0] TPFI CRS_DV Table 72. RMII - 100BASE-TX Receive Timing Parameters Parameter RxData<1:0>, CRS_DV, RXER setup to REFCLK 3 rising edge RxData<1:0>, CRS_DV, RXER hold from REFCLK 3 rising edge Receive start of /J/ to CRS_DV asserted Receive start of /T/ to CRS_DV de-asserted 1. Typical values are at 25 ° ...
Page 191
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 52. RMII - 100BASE-TX Transmit Timing REFCLK TxData(1:0) TPFO TxEN Table 73. RMII - 100BASE-TX Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TxEN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency) 1. Typical values are at 25 ° ...
Page 192
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 53. RMII - 100BASE-FX Receive Timing REFCLK RxData[1:0] TPFI CRS_DV Table 74. RMII - 100BASE-FX Receive Timing Parameters Parameter RxData<1:0>, CRS_DV, RXER setup to 3 REFCLK rising edge RxData<1:0>, CRS_DV, RXER hold from 3 REFCLK rising edge ...
Page 193
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 54. RMII - 100BASE-FX Transmit Timing REFCLK TxData(1:0) TPFO TxEN Table 75. RMII - 100BASE-FX Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TX-EN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency) 1. Typical values are at 25 ° ...
Page 194
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 55. RMII - 10BASE-T Receive Timing REFCLK RxData[1:0] TPFI CRS_DV Table 76. RMII - 10BASE-T Receive Timing Parameters Parameter RxData<1:0>, CRS_DV setup to REFCLK rising 3 edge RxData<1:0>, CRS_DV hold from REFCLK rising 3 edge TPFI in to CRS_DV asserted TPFI quiet to CRS_DV de-asserted 1. Typical values are at 25 ° ...
Page 195
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 56. RMII - 10BASE-T Transmit Timing REFCLK TxData(1:0) TPFO TxEN Table 77. RMII - 10BASE-T Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TxEN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency) 1. Typical values are at 25 ° ...
Page 196
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 57. Auto-Negotiation and Fast Link Pulse Timing Clock Pulse TPFOP Figure 58. Fast Link Pulse Timing FLP Burst TPFOP Table 78. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse ...
Page 197
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 59. MDIO Write Timing (MDIO Sourced by MAC) MDC MDIO Figure 60. MDIO Read Timing (MDIO Sourced by PHY) MDC MDIO Table 79. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, ...
Page 198
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 61. Power-Up Timing Table 80. Power-Up Timing Parameters Parameter Voltage Threshold Power-up recovery time 2 Software power-down 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing ...
Page 199
... Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto- Negotiation” sections of the IEEE 802.3 standard. Additional registers (16 through 21, 25, 27, and 29) are defined in accordance with the IEEE 802.3 standard for adding unique chip functions ...
Page 200
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 82. Register Set (Sheet Address Register Name 27 “Trim Enable Register (Address 27, Hex 1B)” 28 Reserved 29 “Cable Diagnostics Register (Address 29, Hex 1D)” Reserved Table 83. Control Register (Address 0) (Sheet Bit Name 15 RESET_L 6 14 Loopback 13 Speed Selection ...