FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 198

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FWLXT9785BC.A4

Manufacturer Part Number
FWLXT9785BC.A4
Description
Manufacturer
Intel
Datasheet

Specifications of FWLXT9785BC.A4

Lead Free Status / RoHS Status
Not Compliant
198
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 61. Power-Up Timing
Table 80. Power-Up Timing Parameters
Figure 62. RESET_L Recovery Timing
Table 81. RESET_L Recovery Timing Parameters
Voltage Threshold
Power-up recovery time
Software power-down
Reset pulse width
Reset recovery delay
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
2. The minimum time required between bringing up consecutive ports powered down by Register bit 0.11, or
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
a software or hardware reset.
testing.
Parameter
Parameter
2
MDIO,etc
RESET
MDIO,etc
tRcdly
t
VCC
Sym
Sym
t
SPDR
tPW
PDR
v1
Min
100
Min
2.1
0.4
20
10
Typ
Typ
v1
1
1
tPDR
tPW
Max
Max
Units
ms
ms
V
Units
ms
ns
tRcdly
Revision Date: 30-May-2006
Document Number: 249241
Test Conditions
Test Conditions
Revision Number: 010
Datasheet

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