FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 140

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

140
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.8
4.8.1
Figure 22. SS-SMII Transmit Timing
Figure 23. SS-SMII Receive Timing
Note:
RMII Operation
The LXT9785/LXT9785E provides an independent Reduced MII port for each network port. Each
RMII uses four signals to pass received data to the MAC: RxDatan<1:0>, RxERn, and CRS_DVn
(where n reflects the port number). Three signals are used to transmit data from the MAC:
TxDatan_<1:0> and TxENn. Both receive and transmit signals are clocked by REFCLK. Data
transmission across the RMII is implemented in di-bit pairs which equal a 4-bit wide nibble.
The BGA15 package does not support the RMII interface.
RMII Reference Clock
The LXT9785/LXT9785E requires a 50 MHz reference clock (REFCLK). The device samples the
RMII input signals on the rising edge of REFCLK and drives RMII output signals on the falling
edge.
TxCLK
TxSYNC
TxData
TxCLK
TxSYNC
TxData
All signals are synchronous to the clock
RxCLK
RxData
RxSYNC
RxCLK
All signals are synchronous to the clock
RxData
RxSYNC
TXER TXEN
TXER
CRS RXDV
CRS
TXEN
RXDV
Frcerr Speed
TXD0 TXD1
RXER Speed
RXD0 RXD1
TXD2
Dplx
RXD2
Dplx
TXD3 TXD4 TXD5
LINK
RXD3 RXD4 RXD5
LINK
Jabr
Jabr
UPnib
TXD6
RXD6
FlsCar
TXD7
RXD7
TXER
TXER
Revision Date: 30-May-2006
CRS
CRS
Document Number: 249241
Revision Number: 010
Datasheet