FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 180

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

180
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 41. SMII - 100BASE-FX Receive Timing
Table 62. SMII - 100BASE-FX Receive Timing Parameters
RxData output delay from REFCLK
rising edge
RxData Rise/Fall Time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-
asserted
SYNC setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
REFCLK
RxData
SYNC
default configuration of 00 (32 bits of initial fill).
TPFI
Parameter
t
3
t
5
Sym
t1
t2
t3
t4
t5
t6
t
6
Min
1.5
1.5
1.0
–
–
–
t
1
Typ
18
23
–
1
–
–
1
t
2
Max
26
27
5
–
–
–
Units
BT
BT
ns
ns
ns
ns
2
2
t
4
Revision Date: 30-May-2006
Document Number: 249241
Minimum C
Maximum C
Synchronous
sampling of SMII
Synchronous
sampling of SMII
Test Conditions
Revision Number: 010
Datasheet
–
–
–
L
L
= 5 pF
= 20 pF