FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 210

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

210
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 2 of 2)
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
Bit
2:0
4
3
time. Intel recommends that the register status be read on completion of reset.
the pin(s) are latched at startup or hardware reset.
Pause hardware configuration pin. The default for the BGA15 package is 0.
Name
Pause
Error
Reserved
Description
0 = The LXT9785/LXT9785E is not Pause capable
1 = The LXT9785/LXT9785E is pause capable
NOTE: This bit is not affected by Register bit 4.10.
NOTE: The default for the BGA15 package is 0.
0 = No error occurred
1 = Error Occurred (remote fault, RxERCntFUL, FIFO
NOTE: The register is cleared when the registers that
Write as 0, ignore on Read.
error, jabber, parallel detect fault)
generated the error condition are read.
Revision Date: 30-May-2006
Document Number: 249241
Type
Revision Number: 010
R
R
R
1
Datasheet
Default
LSHR
0
0
4,5
2