FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 182

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

182
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 43. SMII - 10BASE-T Receive Timing
Table 64. SMII - 10BASE-T Receive Timing Parameters
RxData output delay from
REFCLK rising edge
RxData Rise/Fall Time
Receive Start-of-Frame to CRS
asserted
Receive Start-of-Idle to CRS
de-asserted
SYNC setup to REFCLK rising
edge
SYNC hold from REFCLK rising
edge
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
REFCLK
RxData
SYNC
default configuration of 00 (32 bits of initial fill).
TPFI
Parameter
t
3
t1
t2
t3
t4
t5
t6
Sym
t
5
1.5
–
–
–
1.5
1.0
Min
t
6
–
1
17
17
–
–
Typ
1
t
1
5
–
21
18
–
–
Max
ns
ns
BT
BT
ns
ns
Units
t
3
3
2
Minimum C
Maximum C
Synchronous sampling of SMII
Synchronous sampling of SMII
Test Conditions
Revision Date: 30-May-2006
t
4
Document Number: 249241
L
L
= 5 pF
= 20 pF
Revision Number: 010
–
–
–
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