FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 108

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

108
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.6
3.6.1
3.6.2
Table 39. Intel
BGA15 Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
Signal Descriptions – SMII and SS-SMII Configurations
Table 39
•
•
•
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and
RxData2_0 and RxData2_1.
®
REFCLK1
REFCLK0
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
Symbol
LXT9785 BGA15 Signal Descriptions (Sheet 1 of 7)
SYNC
provides the BGA15 signal descriptions.
Designation
BGA15 Ball
G3,
N4,
N2,
K3,
E2,
D3,
J1,
A5
C3
L4
K1
SMII/SS-SMII Common Signal Descriptions
SMII Specific Signal Descriptions
Type
I, ID
I, ID
I
Signal Description
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to
Requirements” on page 124
requirements.
SMII Synchronization.
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII.
Section 4.4.2, “Clock/SYNC
for detailed clock
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
Datasheet