FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 86

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 28. MDIO Control Interface Signals – BGA23
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. MDIO[0:1] and MDINT[0:1]_L outputs are three-stated in H/W Power-Down mode and during H/W reset.
4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
BGA23
A10
B10
F3,
F1,
E1,
C9
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
where X is the register number (0-32) and Y is the bit number (0-15).
L1
Designation
Ball/Pin
PQFP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
64
25
67
26
63
24
84
MDINT0_L
MDINT1_L
Symbol
MDIO0
MDIO1
MDDIS
MDC0
MDC1
OD, TS, SL,
I/O, TS, SL,
I, ST, ID
I, ST, ID
Type
IP
IP
1
Signal Description
Management Data Input/Output.
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Only
MDIO0 is used when 1x8 port sectionalization is
selected. In 2x4 port sectionalization mode, MDIO0
accesses ports 0-3 and MDIO1 accesses ports 4-7.
Refer to
on page
Management Data Interrupt.
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Only MDINT0_L is used
when 1x8 port sectionalization is selected.
sectionalization mode, MDINT0_L is associated with
ports 0-3 and MDINT1_L is associated with ports 4-7.
Refer to
on page
Management Data Clock.
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port sectionalization
mode, MDC0 clocks ports 0-3 register accesses and
MDC1 clocks ports 4-7 register accesses. Refer to
Figure 21 “Typical SS-SMII Quad Sectionalization” on
page
Management Disable.
When MDDIS is tied High, the MDIO port is completely
disabled and the Hardware Control Interface pins set
their respective bits at power up and reset.
When MDDIS is pulled Low at power up or reset, via the
internal pull-down resistor or by tieing it to ground, the
Hardware Control Interface Pins control only the initial
or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts
to the MDIO serial channel.
139.
139.
139.
Figure 21 “Typical SS-SMII Quad Sectionalization”
Figure 21 “Typical SS-SMII Quad Sectionalization”
2,3,4
In 2x4 port
86