FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 5

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

5.0
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
4.10
4.11
4.12
4.13
4.14
Application Information ............................................................................................................ 164
5.1
5.2
4.9.1
4.9.2
4.9.3
10 Mbps Operation ........................................................................................................... 149
4.10.1 Preamble Handling .............................................................................................. 149
4.10.2 Dribble Bits .......................................................................................................... 150
4.10.3 Link Test .............................................................................................................. 150
4.10.4 Jabber ..................................................................................................................150
DTE Discovery Process .................................................................................................... 151
4.11.1 Definitions ............................................................................................................ 151
4.11.2 Interaction between Processor, MAC, and PHY ..................................................152
4.11.3 Management Interface and Control .....................................................................152
4.11.4 DTE Discovery Process Flow .............................................................................. 153
4.11.5 DTE Discovery Behavior...................................................................................... 154
Monitoring Operations ......................................................................................................156
4.12.1 Monitoring Auto-Negotiation ................................................................................ 156
4.12.2 Per-Port LED Driver Functions ............................................................................156
4.12.3 Out-of-Band Signaling ......................................................................................... 157
4.12.4 Boundary Scan Interface ..................................................................................... 158
4.12.5 State Machine ......................................................................................................158
4.12.6 Instruction Register .............................................................................................. 158
4.12.7 Boundary Scan Register ...................................................................................... 158
4.13.1 Features............................................................................................................... 159
4.13.2 Operation .............................................................................................................159
4.13.3 Implementation Considerations ........................................................................... 160
4.13.4 Basic Implementation ..........................................................................................160
Link Hold-Off Overview ..................................................................................................... 161
4.14.1 Features............................................................................................................... 161
4.14.2 Operation .............................................................................................................162
Design Recommendations................................................................................................ 164
General Design Guidelines ...............................................................................................164
5.2.1
5.2.2
5.2.3
5.2.4
Cable Diagnostics Overview ............................................................................................. 159
100BASE-X Network Operations ......................................................................... 144
100BASE-X Protocol Sublayer Operations.......................................................... 144
4.9.2.1
PMA Sublayer ......................................................................................................146
4.9.3.1
4.9.3.2
4.9.3.3
4.9.3.4
4.9.3.5
4.9.3.6
4.9.3.7
4.10.3.1 Link Failure ..........................................................................................150
4.13.2.1 Short and Long Cable Testing Requirements ......................................159
4.13.2.2 Precision .............................................................................................. 159
Power Supply Filtering ......................................................................................... 164
Power and Ground Plane Layout Considerations................................................ 165
5.2.2.1
MII Terminations .................................................................................................. 165
Twisted-Pair Interface ..........................................................................................165
5.2.4.1
PCS Sublayer ...................................................................................... 144
Link ......................................................................................................147
Link Failure Override............................................................................147
Carrier Sense/Data Valid (RMII) .......................................................... 147
Carrier Sense (SMII) ............................................................................147
Receive Data Valid (SMII).................................................................... 147
Twisted-Pair PMD Sublayer ................................................................. 148
Fiber PMD Sublayer............................................................................. 148
Chassis Ground ...................................................................................165
Magnetic Requirements .......................................................................166
Contents
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