HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 111

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 39. Intel
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
MODESEL_1
MODESEL_0
TxSLEW_0
TxSLEW_1
®
RESET_L
Symbol
ADD_4
ADD_3
LXT9785 BGA15 Signal Descriptions (Sheet 4 of 7)
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Designation
BGA15 Ball
M11,
N10,
M12
C10
P10
C9,
E8
I, ST, ID
I, ST, ID
I, ST, ID
I, ST, IP
Type
Signal Description
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at that
time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read and
overwritten after startup / reset.
These pins select the TX output slew rate for all ports (rise
and fall time) as follows:
TxSLEW_1
Reset.
This active low input is ORed with the control register Reset
Register bit 0.15. When held Low, all outputs are forced to
inactive state.
Pin is not on JTAG chain.
Address <4:3>.
Sets base address to one of the following four possible
addresses:
Each port adds its port number (starting with 0) to this
address to determine its PHY address.
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = Reserved
01 = SMII
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all SMII or SS-SMII.
• 00000
• 01000
• 10000
• 11000
0
0
1
1
TxSLEW_0
0
1
0
1
Slew Rate (Rise and Fall
Time)
3.3 ns
3.6 ns
3.9 ns
4.2 ns
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