HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 130

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

130
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.6.1.6
4.7
Figure 14. Auto-Negotiation Operation
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the
auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced
link partner, link is not established. The IEEE Standard prevents forced full-duplex-to-half-duplex
link connections.
Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode
With auto MDI/MDIX hardware enabled, end users experience reliable link establishment under all
settings of auto MDI/MDIX and speed between the LXT9785/LXT9785E and its link partners. As
stated in the IEEE clauses 40.4.5.1 (Auto MDI/MDIX) and 28.3.2 (Parallel Detect), when ports are
forced to 10 Mbps or 100 Mbps and auto MDI/MDIX is enabled, and the port is connected to a
partner with auto-negotiation enabled, an undefined condition exists between the IEEE auto MDIX
and Parallel Detect specifications. Link may not occur according to the IEEE specification.
During this undefined condition, when the LXT9785/LXT9785E is set to 10 Mbps or 100 Mbps
and auto MDI/MDIX is enabled, the LXT9785/LXT9785E and the link partner auto-negotiation
processes are expected to be skewed enough to establish link in all but the rarest cases. Auto MDI/
MDIX is configured through hardware and software. If auto MDI/MDIX operation is desired in
forced modes, disabling auto MDI/MDIX using the software programming can aid link
establishment.
Serial MII Operation
The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial
MII (SMII). The SMII performs the following functions:
•
•
•
Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.
Allows a multi-port MAC/PHY communication with one system clock.
Operates in both half and full-duplex.
Auto-Negotiation
Go To Forced
Settings
Disable
Done
0.12 = 0
Power-Up, Reset,
Link Failure
Check Value
Attempt Auto-
Start
0.12
Negotiation
0.12 = 1
YES
Listen for 100TX
Auto-Neg/Parallel Detection
Idle Symbols
Link Set?
Enable
NO
Revision Date: 30-May-2006
Listen for 10T
Link Pulses
Document Number: 249241
Revision Number: 010
Datasheet