HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 200

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

200
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 82. Register Set (Sheet 2 of 2)
Table 83. Control Register (Address 0) (Sheet 1 of 2)
Address
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
6. Link Status is reported in 10 Mbps mode as down and in 100 Mbps mode as up in loopback mode.
30 - 31
14
Bit
15
13
12
10
11
9
8
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
the pin(s) are latched at startup or hardware reset.
“Global Hardware Configuration Settings” on page
Register bits 17.12 (Receive Status) and 17.13 (Transmit Status) are not updated in 10 Mbps loopback
mode.
27
28
29
6
Name
RESET_L
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Isolate
Restart
Auto-Negotiation
Duplex Mode
Register Name
“Trim Enable Register (Address 27, Hex 1B)”
Reserved
“Cable Diagnostics Register (Address 29, Hex 1D)”
Reserved
Description
0 = Normal operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
Not recommended to enable auto-negotiation
while in internal loopback operation.
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
0 = Normal operation
1 = Power-down
0 = Normal operation
1 = Electrically isolate PHY from RMII/SMII/SS-
0 = Normal operation
1 = Restart auto-negotiation process
0 = Half-duplex
1 = Full-duplex
0.6
1
1
0
0
SMII interfaces
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
128.
Bit Assignments
Refer to
N/A
Refer to
N/A
Revision Date: 30-May-2006
Table 100 on page 217
Document Number: 249241
Table 99 on page 216
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SC
SC
Revision Number: 010
1
Datasheet
LSHR
LSHR
LSHR
LSHR
Default
Table 42,
0
0
0
0
2
3,4
3,4
3,5
3,4