HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 167

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

5.2.6
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Figure 33. LED Circuit
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry.
shows a typical example of an LXT9785/LXT9785E-to-3.3 V fiber transceiver interface.
The following occurs in 5 V fiber transceiver applications as shown in
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry.
shows a typical example of an LXT9785/LXT9785E-to-5 V fiber transceiver interface, while
Figure 38
LED Circuit
Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected through a
current-limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin
drives Low. The open-drain LED pins are 5 V tolerant, allowing use of either a 3.3 V or 5 V rail (a
2.5 V rail is unlikely to work with standard forward voltage LEDs). A 5 V rail eases LED
component selection by allowing more common, high-forward voltage LEDs to be used. Refer to
Figure 33
•
•
•
•
•
•
•
The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver
The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 1.2 V
The signal detect pin on a 5 V fiber transceiver interface should use the logic translator
circuitry as shown in
shows the interface circuitry for the logic translator.
for a circuit illustration.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure
38.
VCCIO < V
Inside
IC
LED
LEDn_m
Outside
R
IC
V
< 5 V + 5%
LED
Figure
37:
Figure 36
Figure 37
167