HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 147

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

4.9.3.1
4.9.3.2
4.9.3.3
4.9.3.4
4.9.3.5
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-
Link
In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler
becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses
lock (<16 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a
robust link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100
Mbps idle patterns will not bring up a 10 Mbps link.
The LXT9785/LXT9785E reports link failure via the Register status bits (1.2, 17.10, and 19.4) and
interrupt functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.
Link Failure Override
The LXT9785/LXT9785E normally transmits 100 Mbps data packets or Idle symbols only if it
detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1
overrides this function, allowing the LXT9785/LXT9785E to transmit data packets even when the
link is down. This feature is provided as a diagnostic tool.
negotiation is enabled, the LXT9785/LXT9785E automatically begins transmitting FLP bursts if
the link goes down.
Carrier Sense/Data Valid (RMII)
The LXT9785/LXT9785E asserts CRS_DV whenever the respective port receiver is in a non-idle
state (as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion
of CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not
complete when CRS_DV is asserted, the LXT9785/LXT9785E outputs 00 on the RxData1:0 lines
until the decoded data are available.
When the line returns to an idle state, CRS_DV is de-asserted synchronously with respect to
REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is de-
asserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals,
CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.
Carrier Sense (SMII)
For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair
causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair
causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received
without /T/R/. In this event, receive error is indicated during the IPG until the next packet is
received.
For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of
an End-of-Frame (EOF) marker.
Receive Data Valid (SMII)
The LXT9785/LXT9785E asserts the RX_DV bit when it receives a valid packet. However,
RxData outputs zeros until the received data are decoded and available for transfer to the controller.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
147