HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 178

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

178
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 39. SMII - 100BASE-TX Receive Timing
Table 60. SMII - 100BASE-TX Receive Timing Parameters
RxData output delay from REFCLK
rising edge
RxData Rise/Fall Time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-
asserted
SYNC setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
REFCLK
testing.
100BASE-TX or 100BASE-FX).
RxData
SYNC
TPFI
default configuration of 00 (32 bits of initial fill).
Parameter
t
3
t
5
Sym
t1
t2
t3
t4
t5
t6
t
6
Min
1.5
1.5
1.0
–
–
–
t
Typ
1
1.0
21
25
–
–
–
1
Max
29
30
5
–
–
–
t
2
Units
BT
BT
ns
ns
ns
ns
2
2
Minimum C
Maximum C
Synchronous sampling of
SMII
Synchronous sampling of
SMII
Revision Date: 30-May-2006
Document Number: 249241
t
Test Conditions
4
Revision Number: 010
L
L
= 5 pF
–
–
–
= 20 pF
Datasheet