HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 84

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 25. SMII/SS-SMII Common Signal Descriptions – BGA23
Table 26. SMII Specific Signal Descriptions – BGA23
BGA23
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode.
BGA23
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware
B13,
D13,
A13,
B14,
C15,
A11,
E14
E12
C16
E16
E2,
C3,
B5,
D8,
E6,
A6,
C2,
A3,
B6,
D9,
Designation
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
reset.
Designation
Ball/Pin
Pin/Ball
PQFP
PQFP
203
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
204
206
198
61
52
42
34
22
13
44
35
55
46
37
28
16
4
6
8
REFCLK0
REFCLK1
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
Symbol
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
Symbol
SYNC0
SYNC1
Type
I, ID
Type
O, TS
I
I, ID
1
1
Signal Description
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to Functional Description for detailed clock
requirements. REFCLK0 and REFCLK1 are always
connected regardless of sectionalization mode.
SMII Synchronization.
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII. SYNC0 is used when 1x8
port sectionalization is selected. SYNC0 and SYNC1 are
to be used when 2x4 port sectionalization is chosen.
Receive Data - Ports 0-7.
These serial output streams provide data received from
the network. The LXT9785/9785E drives the data out
synchronously to RXCLK.
2
Signal Description
2,3
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