HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 186

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

186
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 47. SS-SMII - 100BASE-FX Receive Timing
Table 68. SS-SMII - 100BASE-FX Receive Timing Parameters
REFCLK rising edge to RxCLK rising edge
RxData/RxSYNC output delay from RxCLK
rising edge
RxData/RxSYNC Rise/Fall time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
default configuration of 00 (32 bits of initial fill).
RxSYNC
REFCLK
RxData
RxCLK
Parameter
TPFI
t
4
t
1
Sym
t1
t2
t3
t4
t5
t
2
t
3
Min
1.5
–
–
–
–
t
3
Typ
1.5
18
21
–
1
1
t
3
Max
23
26
5
–
Units
BT
BT
ns
ns
ns
t
2
2
5
Revision Date: 30-May-2006
Document Number: 249241
Minimum C
Maximum C
Test Conditions
Revision Number: 010
Datasheet
–
–
–
–
L
L
= 5pF
= 40pF