HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 120

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

120
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.3.4
4.3.4.1
4.3.4.2
4.3.5
4.3.6
4.3.7
Serial Media Independent Interface (SMII) and Source Synchronous-
Serial Media Independent Interface (SS-SMII)
SMII Interface
The LXT9785/LXT9785E provides an independent serial interface for each network port,
complying with the Serial-MII Specification, Revision 1.2. All SMII ports use a common reference
clock and SYNC signal. The SMII Data Interface exchanges data between the LXT9785/
LXT9785E and multiple Media Access Controllers (MACs). All signals are synchronous to the
reference clock. One SYNC control stream is sourced by the MAC to the PHY. Both the transmit
and receive data streams are segmented into boundaries delimited by the SYNC pulses. This
interface is expected to drive up to 6 inches of trace lengths.
Source Synchronous-
The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to
relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK,
and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and
referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the
MAC and in reference to the REFCLK.
Configuration Management Interface
The LXT9785/LXT9785E provides an MDIO Management Interface and a Hardware Control
Interface (via the CFG pins) for device configuration and management. Mode control selection is
provided via the MDDIS pin as shown in
page
Figure 13 on page
MII Isolate
In applications where the MII must be isolated from the bus, the RMII and the SMII/SS-SMII
configurations can be three-stated using Register 0.10. On each individual port, Register bit 0.10
controls the isolation of the transmit and receive data signals for that port. Register bit 0.10 on ports
0 and 4 isolate the RxCLKn/TxCLKn and SYNC signals.
When 1x8 sectionalization is selected, TxCLK0, TxSYNC0, RxCLK1, and RxSYNC1 are used for
the clocking and synchronization interface. Port 4 controls the isolation of RxCLK0, RxCLK1,
RxSYNC0, and RxSYNC1, and must be used to isolate the receive clock and synchronization
interface.
When 2x4 sectionalization is selected, TxCLK0, TxSNC0, RxCLK0, and TxCLK0 are used for
Port 0 through Port 3 and TxCLK1, TxSYNC1, RxCLK1, and RxSYNC1 are used for Port 4
through Port 7. Port 0 must be isolated to isolate the receive clock and synchronization interface for
Port 0 through Port 3. Port 4 must be isolated to isolate Port 4 through Port 7.
MDIO Management Interface
The LXT9785/LXT9785E supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT9785/LXT9785E. The MDIO interface consists of a
40. When sectionalization (2x4) is selected, separate MDIO interfaces are enabled (see
126).
Serial Media Independent Interface
Table 9, “MDIO Control Interface Signals – PQFP” on
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
Datasheet