HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 194

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HBLXT9785EHC.B2Q E000

Manufacturer Part Number
HBLXT9785EHC.B2Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HBLXT9785EHC.B2Q E000

Lead Free Status / RoHS Status
Not Compliant
194
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 55. RMII - 10BASE-T Receive Timing
Table 76. RMII - 10BASE-T Receive Timing Parameters
RxData<1:0>, CRS_DV setup to REFCLK rising
edge
RxData<1:0>, CRS_DV hold from REFCLK rising
edge
TPFI in to CRS_DV asserted
TPFI quiet to CRS_DV de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
testing.
100BASE-TX or 100BASE-FX).
RxData[1:0]
3
3
CRS_DV
REFCLK
default configuration of 00 (32 bits of initial fill).
TPFI
Parameter
t
3
Sym
t1
t2
t3
t4
t
1
Min
1.5
12
4
2
t
2
Typ
15
3
1
t
4
Max
14
14
16
4
Revision Date: 30-May-2006
Units
BT
BT
Document Number: 249241
ns
ns
2
2
Revision Number: 010
Conditions
Datasheet
Test

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