ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 102

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 94.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
DcEndpointStatusImage register: bit allocation
13.2.4 Validate Endpoint Buffer (R/W: 6FH/61H)
13.2.5 Clear Endpoint Buffer (70H, 72H–7FH)
13.2.6 DcEndpointStatusImage register(D0H–DFH)
EPSTAL
R
7
0
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the
buffer is valid and can be sent to the host, when the next IN token is received. For a
double-buffered endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none
This command unlocks and clears the buffer of the selected OUT endpoint, allowing the
reception of new packets. Reception of a complete packet causes the Buffer Full flag of an
OUT endpoint to be set. Any subsequent packets are refused by returning a NAK
condition, until the buffer is unlocked using this command. For a double-buffered endpoint
this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
This command is used to check the status of the selected endpoint FIFO without clearing
any status or interrupt bits. The command accesses the DcEndpointStatusImage register,
which contains a copy of the DcEndpointStatus register. The bit allocation of the
DcEndpointStatusImage register is shown in
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
Table 95.
Bit
7
6
5
4
EPFULL1
R
6
0
DcEndpointStatusImage register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
EPFULL0
R
5
0
Rev. 04 — 29 January 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled,
0 = not stalled).
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
DATA_PID
R
4
0
WRITE
OVER
USB single-chip host and device controller
Table
R
3
0
94.
SETUPT
R
2
0
Section
Section
ISP1161A1
CPUBUF
© ST-NXP Wireless 2009. All rights reserved.
11.3.6.
R
1
0
11.3.6.
reserved
101 of 140
R
0
0