ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 76

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
7
Table 65.
The HCD must set the byte count into the HcTransferCounter register and check the
HcBufferStatus register before reading from or writing to the buffer. The HCD must write
the command (41H to read, C1H to write) once only, and then read or write both bytes of
the data word. After every read/write, the pointer of ATL buffer RAM will be automatically
increased by two to point to the next data word until it reaches the value of the
HcTransferCounter register; otherwise, an internal EOT signal is not generated to set the
bit 2 (AllEOTInterrupt) of the Hc PInterrupt register and update the HcBufferStatus
register.
The HCD must take care of the difference: the internal buffer RAM is organized in bytes,
so the HCD must write the byte count into the HcTransferCounter register, but the HCD
reads or writes the buffer RAM by 16 bits (by 1 data word).
Bit
15 to 0
6
Symbol
DataWord[15:0]
HcATLBufferPort register: bit description
5
Rev. 04 — 29 January 2009
Description
read/write ATL buffer RAM’s two data bytes.
4
DataWord[7:0]
R/W
00H
USB single-chip host and device controller
3
2
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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