ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 79

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 66.
[1]
[2]
ISP1161A1_4
Product data sheet
Endpoint
identifier
0
0
1 to 14
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration register; see
host (ISP1161A1 transmits); OUT: output from the USB host (ISP1161A1 receives).
Endpoint access and programmability
11.3.1 Endpoints with programmable FIFO size
11.3.2 Endpoint access
11.3.3 Endpoint FIFO size
11.3 Endpoint descriptions
FIFO size
(bytes)
64 (fixed)
64 (fixed)
programmable
A DMA transfer is terminated when any of the following conditions are met:
When the DMA transfer is terminated, the buffer is also cleared (even if the data is not
completely read) and the DMA handler is disabled automatically. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
Each USB device is logically composed of several independent endpoints. An endpoint
acts as a terminus of a communication flow between the host and the device. At design
time each endpoint is assigned a unique number (endpoint identifier, see
combination of the device address (given by the host during enumeration), the endpoint
number and the transfer direction allows each endpoint to be uniquely referenced.
The DC has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either via the
Programmed I/O interface or via DMA.
Table 66
mode access. Endpoints 1 to 14 also support DMA access. DC FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DcDMAConfiguration
register. A detailed description of the DC DMA operation is given in
The size of the FIFO determines the maximum packet size that the hardware can support
for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO
storage, disabled endpoints have zero bytes.
The following bits in the Endpoint Configuration register (ECR) affect FIFO allocation:
•
•
•
[1]
•
•
The DMA count is complete
DMAEN = 0
The DMA controller asserts EOT.
Endpoint enable bit (FIFOEN)
Size bits of an enabled endpoint (FFOSZ[3:0])
lists the endpoint access modes and programmability. All endpoints support I/O
Double buffering I/O mode
no
no
supported
Rev. 04 — 29 January 2009
access
yes
yes
supported
USB single-chip host and device controller
Table 67
DMA mode
access
no
no
supported
lists the programmable FIFO sizes.
Section
13.1.1. IN: input for the USB
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
Endpoint type
control OUT
control IN
programmable
Section
Table
12.
[2]
[2]
66). The
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