ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 61

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ISP1161A1BD,151

Manufacturer Part Number
ISP1161A1BD,151
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1161A1BD,151

Lead Free Status / RoHS Status
Supplier Unconfirmed
Table 34.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:2] register: bit allocation
10.3.4 HcRhPortStatus[1:2] register (R/W [1]:15H/95H, [2]: 16H/96H)
R/W
R/W
R/W
31
23
15
0
0
7
0
Table 33.
The HcRhPortStatus[1:2] register is used to control and report port events on a per-port
basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word is used to reflect the port status, whereas
the upper word reflects the status change bits. Some status bits are implemented with
special write behavior. If a transaction (token through handshake) is in progress when a
write to change port status occurs, the resulting port status change must be postponed
until the transaction completes. Reserved bits should always be written logic 0.
Code (Hex): [1] = 15, [2] = 16 — read
Code (Hex): [1] = 95, [2] = 96 — write
Bit
14 to 2
1
0
reserved
reserved
R/W
R/W
R/W
30
22
14
0
0
6
0
HcRhStatus register: bit description
Symbol
-
OCI
LPS
R/W
R/W
R/W
29
21
13
0
0
5
0
Rev. 04 — 29 January 2009
reserved
Description
reserved
OverCurrentIndicator: This bit reports overcurrent conditions when
global reporting is implemented. When set, an overcurrent condition
exists. When clear, all power operations are normal. If per-port
overcurrent protection is implemented this bit is always logic 0.
On read—LocalPowerStatus: The Root Hub does not support the
local power status feature. Therefore, this bit is always read as logic 0.
On write—ClearGlobalPower: In global power mode
(PowerSwitchingMode = 0), this bit is written to logic 1 to turn off
power to all ports (clear PortPowerStatus). In per-port power mode, it
clears PortPowerStatus only on ports whose
bit PortPowerControlMask is not set. Writing a logic 0 has no effect.
PRSC
PRS
R/W
R/W
R/W
28
20
12
0
0
4
0
reserved
R/W
00H
USB single-chip host and device controller
OCIC
POCI
R/W
R/W
R/W
27
19
11
0
0
3
0
…continued
PSSC
PSS
R/W
R/W
R/W
26
18
10
0
0
2
0
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
PESC
LSDA
R/W
R/W
PES
R/W
25
17
0
9
0
1
0
CSC
CCS
PPS
R/W
R/W
R/W
60 of 140
24
16
0
8
0
0
0

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