ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 53

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 20.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
10.2.1 HcFmInterval register (R/W: 0DH/8DH)
10.2 HC frame counter registers
R/W
R/W
FIT
31
23
15
0
0
7
reserved
The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a
frame (that is, between two consecutive SOFs), and a 15-bit value indicating the
full-speed maximum packet size that the HC may transmit or receive without causing a
scheduling overrun. The HCD may carry out minor adjustments on the FrameInterval by
writing a new value at each SOF. This allows the HC to synchronize with an external clock
source and to adjust any unknown clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Table 21.
Bit
31
30 to 16
15 to 14
13 to 0
R/W
R/W
30
22
14
0
0
6
HcFmInterval register: bit description
Symbol
FIT
FSMPS
[14:0]
-
FI[13:0]
R/W
R/W
29
21
13
0
1
5
Rev. 04 — 29 January 2009
Description
FrameIntervalToggle: The HCD toggles this bit whenever it loads a
new value to FrameInterval.
FSLargestDataPacket (FSMaxPacketSize): Specifies a value which
is loaded into the Largest Data Packet Counter at the beginning of
each frame. The counter value represents the largest amount of data
in bits which can be sent or received by the HC in a single transaction
at any given time without causing a scheduling overrun. The field
value is calculated by the HCD.
reserved
FrameInterval: Specifies the interval between two consecutive SOFs
in bit times. The default value is 11999. The HCD must save the
current value of this field before resetting the HC. Setting the
HostControllerReset field of the HcCommandStatus register will cause
the HC to reset this field to its default value. HCD may choose to
restore the saved value upon completing the reset sequence.
R/W
R/W
28
20
12
0
0
4
FSMPS[7:0]
FI[7:0]
DFH
R/W
R/W
00H
FSMPS[14:8]
USB single-chip host and device controller
R/W
R/W
27
19
11
0
1
3
FI[13:8]
R/W
R/W
26
18
10
0
1
2
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
25
17
0
9
1
1
R/W
R/W
52 of 140
24
16
0
8
0
0