ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 127

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
21.2 Interfacing a ISP1161A1 with a SH7709 RISC processor
21.3 Typical software model
This section shows a typical interface circuit between the ISP1161A1 and a RISC
processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The
main ISP1161A1 signals to be taken into consideration for connecting to a SH7709 RISC
processor are:
Remark: SH7709’s system clock input is for reference only. Refer to SH7709’s
specification for its actual use.
The ISP1161A1 can work under either 3.3 V or 5.0 V power supply; however, its internal
core works at 3.3 V. When using 3.3 V as the power supply input, the internal DC/DC
regulator will be bypassed. It is best to connect all four power supply pins (V
V
the ISP1161A1’s I/O pins are 5 V tolerant. This feature allows the ISP1161A1 the flexibility
to be used in an embedded system under either a 3.3 V or a 5 V power supply.
A typical SH7709 interface circuit is shown in
This section shows a typical software requirement for an embedded system that
incorporates the ISP1161A1. The software model for a Digital Still Camera (DSC) is used
as the example for illustration (as shown in
software are required to make full use of the features in the ISP1161A1: the host stack
hold1
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A 16-bit data bus: D[15:0] for the ISP1161A1. The ISP1161A1 is ‘little endian’
compatible.
Two address lines A1 and A0 are needed for a complete addressing of the
ISP1161A1 internal registers:
– A1 = 0 and A0 = 0 will select the Data Port of the Host Controller
– A1 = 0 and A0 = 1 will select the Command Port of the Host Controller
– A1 = 1 and A0 = 0 will select the Data Port of the Device Controller
– A1 = 1 and A0 = 1 will select the Command Port of the Device Controller
The CS line is used for chip selection of the ISP1161A1 in a certain address range of
the RISC system. This signal is active LOW.
RD and WR are common read and write signals. These signals are active LOW.
There are two DMA channel standard control lines:
– DREQ1 and DACK1
– DREQ2 and DACK2
(in each case one channel is used by the HC and the other channel is used by
the DC). These signals have programmable active levels.
Two interrupt lines: INT1 (used by the HC) and INT2 (used by the device controller).
Both have programmable level/edge and polarity (active HIGH or LOW).
The internal 15 k pull-down resistors are used for the HC’s two USB downstream
ports.
The RESET signal is active LOW.
and V
hold2
) to the 3.3 V power supply (for more information, see
Rev. 04 — 29 January 2009
USB single-chip host and device controller
Figure
Figure
65). Two components of system
64.
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
Section
CC
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14). All of
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reg(3.3)
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