ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 92

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 75.
[1]
[2]
[3]
[4]
[5]
[6]
ISP1161A1_4
Product data sheet
Name
General commands
Read Control OUT Error
Code
Read Control IN Error Code
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read Scratch register
Read Frame Number
Read Chip ID
Read Interrupt register
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1)/2.
Validating an OUT endpoint buffer causes unpredictable behavior of the ISP1161A1’s DC.
Clearing an IN endpoint buffer causes unpredictable behavior of the ISP1161A1’s DC.
Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
During isochronous transfer in 16-bit mode, because N
DC command and register summary
13.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH)
13.1 Initialization commands
Initialization commands are used during the enumeration process of the USB network.
These commands are used to configure and enable the embedded endpoints. They also
serve to set the USB assigned address of the ISP1161A1’s DC and to perform a device
reset.
This command is used to access the Endpoint Configuration register (ECR) of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN),
FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit
allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization sequence
and be configured with their default values (see
starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the allocated
memory (size, enable/disable), the FIFO memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Destination
DcErrorCode register
endpoint 0 OUT
DcErrorCode register
endpoint 0 IN
DcErrorCode register
endpoint 1 to 14
all registers with write
access
DcScratch register
DcFrameNumber register
DcChipID register
DcInterrupt register
Rev. 04 — 29 January 2009
Table
…continued
1023, the firmware must take care of the upper byte.
76. A bus reset will disable all endpoints.
Code
(Hex)
A0
A1
A2 to AF
B0
B2/B3
B4
B5
C0
USB single-chip host and device controller
Transaction
read 1 word
read 1 word
read 1 word
write 1 word
write/read 1 word
read 1 word
read 1 word
read 2 words
Table
66). Automatic FIFO allocation
[5]
[5]
[5]
[1]
Reference
Section 13.3.1 on page 102
Section 13.3.2 on page 103
Section 13.3.3 on page 104
Section 13.3.4 on page 104
Section 13.3.5 on page 105
Section 13.3.6 on page 106
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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