ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 88

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
12.4.1.1 External EOT
12.4.1 Bulk endpoints
12.4 End-Of-Transfer conditions
Table 72.
In the DACK-only mode, the ISP1161A1’s DC uses the DACK2 signal as a data strobe.
Input signals RD and WR are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW and MEMR signals: the RD and WR signals are also used as memory data
strobes.
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConfiguration register, see
When reading from an OUT endpoint, an external EOT will stop the DMA operation and
clear any remaining data in the current FIFO. For a double- buffered endpoint the other
(inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet
in the FIFO (even if it is smaller than the maximum packet size) will be sent to the USB
host at the next IN token.
Symbol
EOT
RD
WR
Fig 41. ISP1161A1’s device controller in DACK-only DMA mode.
•
•
•
•
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
DACK-only mode: pin functions
Description
End-Of-Transfer
read strobe
write strobe
CONTROLLER
ISP1161A1
DEVICE
D0 to D15
DREQ2
DACK2
Rev. 04 — 29 January 2009
I/O
I
I
I
RAM
…continued
USB single-chip host and device controller
DREQ
DACK
RD
WR
CONTROLLER
Function
DMA controller terminates the transfer
not used
not used
DMA
HLDA
HRQ
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
HRQ
HLDA
Table
CPU
004aaa186
86):
87 of 140