ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 93

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 76.
Table 78.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcEndpointConfiguration register: bit allocation
DcAddress register: bit allocation
13.1.2 DcAddress register (R/W: B7H/B6H)
13.1.3 DcMode register (R/W: B9H/B8H)
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
Transaction — write/read 1 word
Table 77.
This command is used to set the USB assigned address in the DcAddress register and
enable the USB device. The DcAddress register bit allocation is shown in
A USB bus reset sets the device address to 00H (internally) and enables the device. The
value of the DcAddress register (accessible by the microcontroller) is not altered by the
bus reset. In response to the standard USB request, Set Address, the firmware must issue
a Write Device Address command, followed by sending an empty packet to the host. The
new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read DcAddress register
Transaction — write/read 1 word
Table 79.
This command is used to access the ISP1161A1’s DcMode register, which consists of
1 byte (for bit allocation: see
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
DcEndpointConfiguration register: bit description
DcAddress register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
DBLBUF
R/W
R/W
5
0
5
0
Rev. 04 — 29 January 2009
Description
A logic 1 indicates an enabled FIFO with allocated memory. A
logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
A logic 1 indicates that this endpoint has double buffering.
A logic 1 indicates an isochronous endpoint. A logic 0 indicates a
bulk or interrupt endpoint.
Selects the FIFO size according to
Description
A logic 1 enables the device.
This field specifies the USB device address.
Table
FFOISO
R/W
R/W
4
0
4
0
79). In 16-bit bus mode the upper byte is ignored.
DEVADR[6:0]
USB single-chip host and device controller
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
FFOSZ[3:0]
Table 67
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
1
0
1
0
Table
78.
R/W
R/W
92 of 140
0
0
0
0