ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 82

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
11.4.1 Suspend conditions
11.4 Suspend and resume
The ISP1161A1 DC detects a USB suspend status when a constant idle state is present
on the USB bus for more than 3 ms.
The bus-powered devices that are suspended must not consume more than 500 A of
current. This is achieved by shutting down power to system components or supplying
them with a reduced voltage.
The steps leading up to suspend status are as follows:
Figure 38
1. On detecting a wakeup-to-suspend transition, the ISP1161A1 DC sets bit SUSPND in
2. When the firmware detects a suspend condition, it must prepare all system
3. In the interrupt service routine, the firmware must check the current status of the USB
4. To meet the suspend current requirements for a bus-powered device, the internal
5. When the firmware has set and cleared bit GOSUSP in the DcMode register, the
the DcInterrupt register. This will generate an interrupt if bit IESUSP in the
DcInterruptEnable register is set.
components for the suspend state:
a. All signals connected to the ISP1161A1 DC must enter appropriate states to meet
b. All input pins of the ISP1161A1 DC must have a CMOS LOW or HIGH level.
bus. When bit BUSTATUS in the DcInterrupt register is logic 0, the USB bus has left
the suspend mode and the process must be aborted. Otherwise, the next step can be
executed.
clocks must be switched off by clearing bit CLKRUN in the DcHardwareConfiguration
register.
ISP1161A1 enters the suspend state. In powered-off application, the ISP1161A1 DC
asserts output SUSPEND and switches off the internal clocks after 2 ms.
the power consumption requirements of the suspend state.
shows a typical timing diagram.
Rev. 04 — 29 January 2009
USB single-chip host and device controller
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
81 of 140