ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 12

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7. Functional description
ISP1161A1_4
Product data sheet
7.1 PLL clock multiplier
7.2 Bit clock recovery
7.3 Analog transceivers
7.4 ST-NXP Wireless Serial Interface Engine (SIE)
7.5 SoftConnect
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
The bit clock recovery circuit recovers the clock from the incoming USB data stream using
a 4 times over-sampling principle. It is able to track jitter and frequency drift as specified in
the Universal Serial Bus Specification Rev. 2.0.
Three sets of transceivers are embedded in the chip: two are used for downstream ports
with USB connector type A; one is used for upstream port with USB connector type B. The
integrated transceivers are compliant with the Universal Serial Bus Specification Rev. 2.0.
They interface directly with the USB connectors and cables through external termination
resistors.
The ST-NXP Wireless SIE implements the full USB protocol layer. It is completely
hardwired for speed and needs no firmware intervention. The functions of this block
include: synchronization pattern recognition, parallel/serial conversion, bit (de)stuffing,
CRC checking/generation, Packet IDentifier (PID) verification/generation, address
recognition, handshake evaluation/generation. There are separate SIEs in the HC and
the DC.
The connection to the USB is accomplished by bringing D+ (for full-speed USB devices)
HIGH through a 1.5 k
is integrated on-chip and is not connected to V
established through a command sent by the external/system microcontroller. This allows
the system microcontroller to complete its initialization sequence before deciding to
establish connection with the USB. Re-initialization of the USB connection can also be
performed without disconnecting the cable.
The ISP1161A1 DC will check for USB V
established. V
Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 %
tolerance specified by the USB specification. However, the overall voltage specification for
the connection can still be met with a good margin. The decision to make use of this
feature lies with the USB equipment designer.
BUS
sensing is provided through pin D_VBUS.
Rev. 04 — 29 January 2009
pull-up resistor. In the ISP1161A1 DC, the 1.5 k
BUS
USB single-chip host and device controller
availability before the connection can be
CC
by default. The connection is
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
pull-up resistor
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