LSI53C825AJ LSI, LSI53C825AJ Datasheet
LSI53C825AJ
Specifications of LSI53C825AJ
Related parts for LSI53C825AJ
LSI53C825AJ Summary of contents
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... TECHNICAL MANUAL LSI53C825A/825AE PCI to SCSI I/O Processor Version 3 ® S14058 ...
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... LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties ...
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... Preface This book is the primary reference and technical manual for the LSI Logic LSI53C825A/825AE PCI to SCSI I/O Processor. It contains a complete functional description for the LSI53C825A/825AE and includes complete physical and electrical specifications for the LSI53C825A/825AE. Audience This technical manual is intended for system designers and programmers who are using this device to design a SCSI port for PCI-based personal computers, workstations, or embedded applications ...
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... Chapter 6, instructions that are supported by the LSI53C825A. Appendix A, Register Appendix B, External Memory Interface Diagram contains several example interface drawings to connect the LSI53C825A to an external ROM. Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3 ...
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... Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision Date 1.0 6/95 2.0 3/96 3.0 12/97 3.1 1/01 Preface Remarks Revision 1.0 Revision 2.0 Revision 3.0 Product names changed from SYM to LSI. v ...
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Preface ...
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... Contents Chapter 1 Introduction 1.1 General Description 1.2 Package and Feature Options 1.2.1 1.3 TolerANT 1.4 LSI53C825A Benefits Summary 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 Chapter 2 Functional Description 2.1 PCI Addressing 2.1.1 2.1.2 2.1.3 2.2 SCSI Functional Description 2.2.1 2.2.2 2 ...
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Power Management 2.5.1 2.5.2 Chapter 3 Signal Descriptions 3.1 PCI Bus Interface Signals 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.2 MAD Bus ...
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Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Level Register Interface Mode 5.2 High Level SCSI SCRIPTS Mode 5.2.1 5.3 Block Move Instructions 5.3.1 5.3.2 5.4 I/O Instruction 5.4.1 5.4.2 5.5 Read/Write Instructions 5.5.1 5.5.2 5.5.3 5.5.4 5.6 Transfer Control ...
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... Regulated Termination 2.5 Determining the Synchronous Transfer Rate 2.6 Block Move and Chained Block Move Instructions 3.1 LSI53C825A Pin Diagram 3.2 LSI53C825AJ Pin Diagram 3.3 LSI53C825A Functional Signal Grouping 5.1 SCRIPTS Overview 5.2 Block Move Instruction Register 5.3 I/O Instruction Register 5 ...
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... Initiator Asynchronous Send 6.32 Initiator Asynchronous Receive 6.33 Target Asynchronous Send 6.34 Target Asynchronous Receive 6.35 Initiator and Target Synchronous Transfers 6.36 LSI53C825A 160 Pin PQFP (PF) Mechanical Drawing B.1 64 Kbyte Interface with 200 ns Memory Contents 6-11 6-12 6-13 6-15 6-16 6-17 ...
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... SCSI Bus Interface Signals 3.8 Additional Interface Signals 3.9 External Memory Interface Signals 3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only) 3.11 Subsystem Data Configuration Table for the LSI53C825AE (PCI Rev ID 0x26) 3.12 Subsystem Data Configuration Table for the LSI53C825A (PCI Rev ID 0x14) Revision G Only 3 ...
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... IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 6.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4 6.12 Bidirectional Signals—MAD[7:0] 6.13 Input Signals—TDI, TMS, TCK (LSI53C825AJ only) 6.14 Output Signal—TDO (LSI53C825AJ only) 6.15 TolerANT Technology Electrical Characteristics 6.16 External Clock 6.17 Reset Input 6 ...
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Contents ...
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... Chapter 1 Introduction This chapter includes general information about the LSI53C825A and other members of the LSI53C8XX family of PCI to SCSI I/O Processors and contains the following sections: Section 1.1, “General Description” Section 1.2, “Package and Feature Options” Section 1.3, “TolerANT Section 1.4, “LSI53C825A Benefits Summary” ...
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... Package and Feature Options The LSI53C825A is packaged in a 160-pin plastic quad flat pack. The device is also available, as the LSI53C825AJ, with additional pins that support JTAG boundary scan testing. The JTAG boundary scan signals replace the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 pins. The devices that have been upgraded to include the power management features are the LSI53C825AE and LSI53C825AJE ...
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... TolerANT Technology The LSI53C825A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than passively pulled up by terminators. ...
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... SCSI operations. TolerANT input signal filtering is a built-in feature of the LSI53C825A and all LSI Logic fast SCSI devices. On the LSI53C825A, the user may select a filtering period ns, with bit 1 in the Test Two (STEST2) The benefi ...
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... Complies with PCI Bus Power Management Specification (LSI53C825AE), Revision 1.0 1.4.2 PCI Performance To improve PCI performance, the LSI53C825A: Complies with PCI 2.1 specification Bursts 16, 32, 64, or 128 Dwords across PCI bus Supports 32-bit word data bursts with variable burst lengths ...
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... Direct PCI to SCSI connection Reduced SCSI development effort Easily adapted to the ASPI or the ANSI CAM, with SDMS software Compiler compatible with existing LSI53C7XX and LSI53C8XX family SCRIPTS Direct connection to PCI, SCSI SE, and differential buses Development tools and sample SCSI SCRIPTS available ...
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... Flexibility The LSI53C825A contains these flexibility features: High level programming interface (SCSI SCRIPTS) Programs local memory bus Flash memory Big/little endian support Selectable 88-byte or 536-byte DMA FIFO for backward compatibility Tailored SCSI sequences execute from main system RAM or internal SCRIPTS RAM ...
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... SCSI bus signal continuity checking Support for single-step mode operation Test mode (AND tree) to check pin continuity to the board (most package options) JTAG Boundary scan support (LSI53C825AJ only) A system diagram showing the connections of the LSI53C825A with an external ROM or Flash memory is pictured in of the LSI53C825A is pictured in ...
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... Figure 1.1 LSI53C825A External Memory Interface GPIO4 MWE/ MOE/ MCE/ MAD[7:0] PCI Bus MAS0/ LSI53C825A MAS1/ SCSI Bus GPIO2_MAS2/ BIG_LIT LSI53C825A Benefits Summary (Optional Translator HCT374 HCT374 HCT374 (Optional) ROM or Flash Memory D[7:0] A[7:0] A[15:8] A[19:16] 1-9 ...
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... Figure 1.2 External Memory Memory Control Local Bus Memory 1-10 Introduction LSI53C825A Chip Block Diagram PCI PCI Master and Slave Control Block SCSI Data Operating SCRIPTS FIFO Registers Processor 536 Bytes SCSI FIFO and SCSI Control Block TolerANT Drivers and Receivers SCSI Bus Confi ...
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... IDSEL is ignored. The eight lower order addresses are used to select a specific 8-bit register. AD[10:8] are decoded as well, but they must be zero or the LSI53C825A does not respond. According to the PCI specification, AD[10:8] are to be used for multifunction devices. The host processor uses the PCI confi ...
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... At initialization time, each PCI device is assigned a base address (in the case of the LSI53C825A, the upper 24 bits of the address are selected) for memory accesses and I/O accesses. On every access, the LSI53C825A compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase ...
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Table 2.1 PCI Bus Commands and Encoding Types C_BE[3:0] Command Type 0000 Special Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read Cycle 0011 I/O Write Cycle 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved ...
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... Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands. 2.1.3.1 Support for PCI Cache Line Size Register The LSI53C825A supports the PCI specification for an 8-bit Size register in PCI configuration space. It can sense and react to nonaligned addresses corresponding to cache line boundaries ...
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... Note: 2.1.3.3 Alignment The LSI53C825A uses the calculated line size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip attempts to align to the cache boundary by using a “smart aligning” scheme. This means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no overfl ...
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... Alignment stops, and the burst size from then on is switched to 16. 2.1.3.4 Memory Move Misalignment The LSI53C825A does not operate in a cache alignment mode when a Memory Move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. ...
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... Latency – In accordance with the PCI specification, the latency timer is ignored when issuing a Write and Invalidate command such that when a latency time-out occurs, the LSI53C825A continues to transfer up until a cache line boundary. At that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached ...
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... Read Line command is issued. However, the Read Line option operates exactly like the previous LSI53C8XX chips when cache mode is disabled by a CLSE bit reset or when certain conditions exist in the chip (explained below). The Read Line mode is enabled by setting bit 3 in the ...
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... This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C825A supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by ...
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... The LSI53C825A is composed of three functional blocks: the the DMA supported by the SDMS, a complete software package that supports the LSI Logic product line of SCSI processors and controllers. The PCI Bus Power Management this chapter. 2.2.1 SCSI Core The SCSI core supports the 8-bit or 16-bit data bus. It supports SCSI synchronous transfer rates Mbytes/s, and asynchronous transfer rates Mbytes 16-bit wide SCSI bus ...
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... SCSI SCRIPTS are hardware independent, so they can be used interchangeably on any host or CPU system bus. 2.2.4 Internal SCRIPTS RAM The LSI53C825A has 4 Kbytes (1024 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS ...
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... Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus. Other types of access to the RAM by the LSI53C825A use the PCI bus they were external accesses. The MAD5 pin enables the 4 K internal RAM ...
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... Read Line, Read Multiple, and Write and Invalidate commands are not used. The LSI53C825A may flush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. When one of these conditions apply, the contents of the prefetch unit are fl ...
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... Opcode Fetch Burst Capability Setting the Burst Opcode Fetch Enable bit in the register (0x38) causes the LSI53C825A to burst in the first two longwords of all instruction fetches. If the instruction is a memory-to-memory move, the third longword is accessed in a separate ownership. If the instruction is an indirect type, the additional longword is accessed in a subsequent bus ownership ...
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... The LSI53C825A supports a variety of sizes and speeds of expansion ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of pins MAD[3:1] allows the user to define how much external memory is available to the LSI53C825A. associated with the possible values of MAD[3:1]. The MAD[3:1] pins are fully defi ...
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... MAD bus. The internal pull-up resistors are disabled when external pull-down resistors are detected, to reduce current drain. The LSI53C825A allows the system to determine the size of the available external memory using the PCI configuration space. For more information on how this works, refer to the PCI specifi ...
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... Load and Store instructions, refer to SCRIPTS Instruction Set.” 2.4.2 3.3 V/5 V PCI Interface The LSI53C825A can attach directly PCI interface, due to separate used on the universal board recommended by the PCI Special Interest Group. 2.4.3 Additional Access to General Purpose Pins The LSI53C825A can access the GPIO0 and GPIO1 general purpose pins through register bits in the PCI confi ...
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... The device can accept all required boundary scan instructions, as well as the optional CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C825AJ uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register ...
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... Big and Little Endian Support The LSI53C825A supports both big and little endian byte ordering through pin selection. The LSI53C825AJ operates in little endian mode only (the BIG_LIT pin is replaced by one of the JTAG boundary scan signals). In big endian mode, the first byte of an aligned SCSI to PCI transfer is routed to lane three and succeeding transfers are routed to descending lanes ...
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... When the Loopback Enable bit is set in the register, the LSI53C825A allows control of all SCSI signals, whether the LSI53C825A is operating in initiator or target mode. For more information on this mode of operation, refer to the SCSI SCRIPTS Processors Programming Guide . ...
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... Parity Options The LSI53C825A implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the SCSI bus to test parity error recovery procedures. ...
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... SCSI Status Data Latch (SIDL) (SSTAT1), Enables parity checking during master data phases. Set when the LSI53C825A as a master detects that a target device has signaled a parity error during a data phase. By clearing this bit, a Master Data Parity Error will not (DIEN), ...
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... SCSI Interrupt Enable Zero 2.4.8 DMA FIFO The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is illustrated in LSI53C8XX family, the user may set the DMA FIFO size to 88 bytes by clearing the DMA FIFO Size bit, bit 5 in the register. Figure 2.1 ...
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... Data Paths The data path through the LSI53C825A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously. The following steps determine if any bytes remain in the data path when the chip halts an operation: Asynchronous SCSI Send – ...
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Counter (DBC) register from the 7-bit value of the (DFIFO) register. AND the result with 0x7F for a byte count between zero and 88. If the DMA FIFO size is set to 536 bytes (using bit 5 of the Test ...
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Step 2. Read bit 7 in the Step 3. If any wide transfers have been performed using the Chained Synchronous SCSI Receive – Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven least Step ...
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... SCSI bus. Each output is isolated from the power supply to ensure that a powered-down LSI53C825A has no effect on an active SCSI bus (CMOS “voltage feed-through” phenomena). TolerANT technology provides signal filtering at the inputs of SREQ/ and SACK/ to increase immunity to signal refl ...
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... Active HIGH signal used to control direction of the differential drivers for target group signals MSG/, C/D/, I/O/, and REQ/. DIFFSENS Input to the LSI53C825A used to detect the presence device on a differential system logical zero is detected on this pin, then it is assumed that an SE device is on the bus and all SCSI outputs will be 3-stated to avoid damage to the transceiver ...
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... SCSI bus lines. This is very important, as errors may occur during reselection if these lines are left floating. In the LSI53C825AJ, the SDIRP1 pin is replaced by the TCK JTAG signal. If the device is used in a wide differential system, use the SDIRP0 pin to control the direction of the differential transceiver for both the SP0 and SP1 signals ...
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... Functional Description pull-up to the terminator power supply (Term pull-down to ground. Because of the If the LSI53C825A used in a design with only an 8-bit SCSI bus, all 16 data lines still must be terminated or pulled HIGH example differential wiring diagram. shows a Unitrode active terminator. For additional information, ...
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... Figure 2.3 LSI53C825A Differential Wiring Diagram LSI53C8XX SELDIR BSYDIR RSTDIR SEL/ BSY/ RST/ REQ/ VDD ACK/ MSG/ VDD C/D/ I/O/ 1.5 K ATN/ TGS IGS VDD 1.5 K SD[8:15]/ SDP1/ VDD SDIRP0 SDIR7 1.5 K SDIR6 SDIR5 SDIR4 SDIR3 SDIR2 SDIR1 SDIR0 SDP0/ SD7/ ...
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Figure 2.4 Regulated Termination 2 2.85 V REG_OUT DISCONNECT 14 REG_OUT C3 6 DISCONNECT Note SMT 0.1 F SMT 2.2 F SMT 68-pin, ...
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... Set Target instruction. The Selection and Reselection Enable bits (SCID bits 5 and 6, respectively) should both be asserted so that the LSI53C825A may respond as an initiator target. If only selection is enabled, the LSI53C825A cannot be reselected as an initiator. There are also status and interrupt bits in the ...
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SCSI Control Three (SCNTL3) Register, Bits [6:4] The SCF[2:0] bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic. The output from this divider controls the rate at ...
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... The SCRIPTS processor in the LSI53C825A performs most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C825A. 2.4.13.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts ...
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... Reading these registers determines which condition or conditions caused the SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C825A is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt. If the LSI53C825A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO ...
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CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing. The CLF bit is bit 2 in The CSF bit is bit 1 in DSTAT – The interrupt bits. Reading this register determines ...
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... CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C825A has been selected or reselected (SEL or RSL set), when the initiator has asserted ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire. These interrupts are not needed for events that occur during high-level SCRIPTS operation ...
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... Masking an interrupt after IRQ/ is asserted does not cause IRQ deasserted. 2.4.13.5 Stacked Interrupts The LSI53C825A stacks interrupts if they occur one after the other. If the SIP or DIP bits in the then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the ...
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... These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.4.13.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C825A attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction since it is updated when the current instruction is fetched ...
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... All other instructions may halt before completion. 2.4.13.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C825A. It can be repeated during polling or should be called when the IRQ/ pin is asserted during hardware interrupts. 1. Read 2. If the INTF bit is set, it must be written to a one to clear this status. ...
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... Chained Block Moves Since the LSI53C825A has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The chained move (CHMOV) SCRIPTS instruction along with the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the Two (SCNTL2) 2 ...
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SCRIPTS. The bit can also be used by the microprocessor or SCRIPTS for error detection and recovery purposes. 2.4.14.3 SWIDE Register This register stores data for partial byte data transfers. For receive data, the ...
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Whether the WSR bit is set or cleared, when a normal block move instruction is executed, the contents of the register are ignored and the transfer takes place normally. ...
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The Chained Block Move instruction is illustrated in Figure 2.6 Block Move and Chained Block Move Instructions Host Memory 0x03 0x02 0x01 0x00 00 0x07 0x06 0x05 0x04 04 0x0B 0x0A 0x09 0x08 08 0x0F 0x0E 0x0D 0x0C 0C 0x13 ...
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Power Management This feature complies with the PCI Bus Power Management Interface Specification, Revision 1.0. The PCI Function Power States are defined in that specification: D0, D1, D2, and D3. D0 and D3 are required by specification, and D1 ...
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... The pin definitions are presented in Table 3.1 through Table 3.10. The LSI53C825A is a pin-for-pin replacement for the LSI53C825. This chapter is divided into the following sections: Section 3.1, “PCI Bus Interface Signals” Section 3.2, “MAD Bus Programming” LSI53C825A/825AE PCI to SCSI I/O Processor Figure 3 ...
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... Note: The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capacitor values between 0.01 and 0.1 F should provide adequate noise isolation. Because of the number of high current drivers on the LSI53C825A, a multilayer PC board with power and ground planes is required. 3-2 ...
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... Figure 3.2 LSI53C825AJ Pin Diagram C_BE3/ 1 IDSEL 2 AD23 AD22 5 AD21 6 AD20 DD-I AD19 AD18 11 AD17 12 AD16 C_BE2 FRAME/ IRDY TRDY/ 19 DEVSEL DD-I STOP PERR/ 24 PAR/ 25 C_BE1 AD15 28 AD14 29 AD13 AD12 DD-I AD11 34 AD10 35 AD9 AD8 38 C_BE0/ 39 AD7 40 The PCI/SCSI pin definitions are organized into the following functional groups: System, Address/Data, Interface Control, Arbitration, Error Reporting, SCSI, and Optional Interface ...
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... DD 1. These pins can accept a VDD source of 3 Volts. All other VDD pins must be supplied 5 Volts. 3-4 Signal Descriptions LSI53C825A, LSI53C825AJ, LSI53C825AE, and LSI53C825AJE Power and Ground Pins Pin No. Description 4, 10, 14, 18, 23, 27, Ground to the PCI I/O pins 31, 37, 42, 48, 69, 79, ...
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... PAR Data FRAME/ TRDY/ Interface IRDY/ Control STOP/ DEVSEL/ IDSEL REQ/ Arbitration GNT/ PERR/ Error Reporting SERR/ is the functional signal grouping for the LSI53C825A. LSI53C825A SCLK SD[15:0] SDP[1:0] SCTRL SDIR[15:0] SDIRP[1:0] SELDIR RSTDIR BSYDIR IGS TGS TESTIN/ GPIO0_FETCH/ GPIO1_MASTER/ GPIO[4:3] DIFFSENS ...
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... PCI device. All other PCI signals are sampled on the rising edge of CLK, and other timing parameters are defined with respect to this edge. This clock can optionally be used as the SCSI core clock; however, the LSI53C825A is not able to achieve Fast SCSI transfer rates. RST/ 144 I Reset forces the PCI sequencer of each device to a known state ...
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Address and Data Signals Table 3.3 Table 3.3 Address and Data Signals Name Pin No. Type Description AD[31:0] 150, 151, 153, 154, 156, 157, 159, 160 11, 12, 13, 28, 29, 30, 32, 34, ...
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Interface Control Signals Table 3.4 Table 3.4 Interface Control Signals Name Pin No. Type Description FRAME/ 16 S/T/S Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to ...
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Arbitration Signals Table 3.5 Table 3.5 Arbitration Signals Name Pin No. Type Description REQ/ 148 O Request indicates to the arbiter that this agent desires use of the PCI bus. This is a point-to-point signal. Every master has its ...
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... Driver direction control for SCSI data lines. O Driver direction control for SCSI parity signals. In the LSI53C825AJ, this pin is replaced by the TCK JTAG signal. If the device is used in a wide differential system, use the SDIRP0 pin to control the direction of the differential transceiver for both the SP0 and SP1 signals. The SDIRP0 signal is capable of driving both direction inputs from a transceiver ...
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... Additional Interface Signals Table 3.8 Table 3.8 Additional Interface Signals Name Pin No. Type Description TESTIN (Not 57, NA available on LSI53C825AJ) GPIO0_ 53/70/N5 FETCH/ PCI Bus Interface Signals Type Description O Driver Enable Control for SCSI RST/ signal. O Driver Enable Control for SCSI BSY/ signal. ...
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... MASTER/ GPIO[4:3] 71, 70 DIFFSENS 72 MAC/_ 58, NA TESTOUT (Not available on LSI53C825AJ) IRQ/ 52/69/ M5 3-12 Signal Descriptions I/O General purpose I/O pin. Optionally, when driven LOW, indicates that the LSI53C825A is bus master. This pin powers general purpose input. LSI Logic SDMS software supports use of this signal in serial EEPROM applications, when enabled, in combination with the GPIO0 pin ...
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... Name Pin No. Type Description BIG_LIT/ (Not 142, NA available on LSI53C825AJ) PCI Bus Interface Signals I Big_Little Endian Select. When this pin is driven LOW, the LSI53C825A routes the first byte of an aligned SCSI to PCI transfer to byte lane zero of the PCI bus and subsequent bytes received are routed to ascending lanes. An aligned PCI to SCSI transfer routes PCI byte lane zero onto the SCSI bus fi ...
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... Memory Address Strobe 0. This pin is used to latch in the least significant address byte of an external EPROM or flash memory. Since the LSI53C825A moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which are used to assemble 20-bit address for the external memory. ...
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... JTAG Signals Table 3.10 Table 3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only) Name Pin No. TCK 130/130 TMS 57/57 TDI 142/142 TDO 58/58 3.2 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, are also used to program power-up options for the chip ...
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... Subsystem Vendor ID 0x2C Subsystem ID 0x2E 1. The chip revisions before Revision G of the LSI53C825A (PCI Rev ID 0x14) do not support different Subsystem Data Configurations. The registers are hardwired to zero values. MAD[3:1] – used to set the size of the external expansion ROM device attached. Encoding for these pins are listed in ...
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Table 3.13 External Memory Support MAD[3:1] Available Memory Space 000 001 010 011 100 101 110 111 No external memory present MAD[0] – the slow ROM pin. When pulled down, it enables two extra clock cycles of data access time ...
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Signal Descriptions ...
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... PCI-compliant registers is optional. In the LSI53C825A, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C825A are described in this chapter. Reserved bits should not be accessed. LSI53C825A/825AE PCI to SCSI I/O Processor The confi ...
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... If expansion memory is enabled through pull-down resistors on the MAD[7:0] bus. Note: Addresses 0x40–7F are not defined for the LSI53C825A. Addresses 0x48–7F are not defined for the LSI53C825AE. All unsupported registers are not writable and return all zeros when read. ...
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... PCI cycles. When a zero is written to this register, the LSI53C825A is logically disconnected from the PCI bus for all accesses except configuration accesses. In the LSI53C825A, bits 3 through 5 and bit 7 and 9 are not implemented. Bits 10 through 15 are reserved. Configuration Registers ...
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... Reserved Enable Bus Mastering This bit controls the ability of the LSI53C825A to act as a master on the PCI bus. A value of zero disables the device from generating PCI bus master accesses. A value of one allows the LSI53825A to behave as a bus master ...
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... Status register is used to record status information for PCI bus related events. In the LSI53C825A, bits 0 through 4 are reserved and bits and 11 are not implemented by the LSI53C825A. Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a one ...
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... These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. In the LSI53C825A, 0b01 is supported. Data Parity Reported This bit is set when the following three conditions are ...
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... CC[23:0] Configuration Registers RID Revision ID This register specifies a device specific revision identifier. For revision A of the LSI53C825AE, the value of this register is 0x26. CC[23: Class Code This register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifi ...
Page 96
... Cache Line Size Enable (CLSE) bit, bit 7 in the Control (DCNTL) register. Setting this bit causes the LSI53C825A to align to cache line boundaries before allowing any bursting, except during Memory Moves in which the read and write addresses are not aligned to a burst size boundary. For more information on this register, see Section 2.1.3.1, “ ...
Page 97
Register: 0x0E Header Type Read Only 7 0 HT[7:0] Register: 0x10 Base Address Zero (I/O) Read/Write BARZ Register: 0x14 Base Address One (Memory) Read/Write ...
Page 98
... SS MAD[6] and MAD[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. In revisions before Rev the LSI53C825A, the MAD[6] and MAD[4] pins do not support the SSID and SSVID configurations, and only values of 0x0000 can be found in the Subsystem Data register. ...
Page 99
... MAD[6] and MAD[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. In revisions before Revision G of the LSI53C825A, the MAD[6] and MAD[4] pins do not support the SSID and SSVID configurations, and only values of 0x0000 can be found in the Subsystem Data register ...
Page 100
... Expansion ROM Base Address with all ones and then reading back the register. The LSI53C825A will respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size. For example, ...
Page 101
... Min_Gnt This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C25A sets this register to 0x11. Configuration Registers ...
Page 102
... This register is used to specify the desired settings for latency timer values. Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in these registers is in units of 0.25 microseconds. The LSI53C825A sets this register to 0x40. CID 0 ...
Page 103
... PMES[4:0] D2S D1S This register applies to the LSI53C825AE only and indicates the power management capabilities. PMES[4:0] PME Support This field is always set to 00000b because the LSI53C825AE does not provide a PME signal. D2S D2 Support This device does not support the D2 power management state ...
Page 104
... VER[2:0] Register: 0x44 Power Management Control/Status Read Write PST DSCL 0 0 This register applies to the LSI53C825AE only and indicates the power management control and status descriptions. PST DSCL DSLT 4-16 Registers Reserved Device Specific Initialization This bit is cleared to indicate that the LSI53C825A requires no special initialization before the generic class device driver is able to use it ...
Page 105
... PEN PME Enable The LSI53C825A always returns a zero for this bit to indicate that PME assertion is disabled. R Reserved PWS Power State Bits [1:0] are used to determine the current power state for the LSI53C825A. They are used to place the LSI53C825A in a new power state. Power states are defi ...
Page 106
... Operating Registers This section contains descriptions of all LSI53C825A operating registers. Table 4.2, the register map, lists registers by operating and configuration addresses. The terms “set” and “assert” are used to refer to bits that are programmed to a binary one. Similarly, the terms “deassert,” “clear,” and “ ...
Page 107
... Table 4.2 LSI53C825A Register Map 31 SCNTL3 SCNTL2 GPREG SBCL SSTAT2 SSTAT1 Reserved CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SIST1 SIST0 GPCNTL MACNTL RESPID1 RESPID0 STEST3 STEST2 Reserved Reserved Reserved Operating Registers 16 15 SCNTL1 SDID SXFER SSID SOCL SSTAT0 DSA CTEST1 TEMP ...
Page 108
... Full arbitration, selection/reselection Simple Arbitration 1. The LSI53C825A waits for a bus free condition to occur asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device, the LSI53C825A deasserts SBSY/, deasserts its ID, and sets the Lost Arbitration bit ...
Page 109
... Time-Out bit is set in the (SIST1) START Start Sequence When this bit is set, the LSI53C825A starts the arbitration sequence indicated by the Arbitration Mode bits. The Start Sequence bit is accessed directly in low level mode; during SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor. An arbitration sequence should ...
Page 110
... AAP 4-22 Registers Select with SATN Start Sequence When this bit is set and the LSI53C825A is in the initiator mode, the SATN/ signal is asserted during LSI53C825A selection of a SCSI target device. This is to inform the target that the LSI53C825A has a message to send ...
Page 111
... When the LSI53C825A is an initiator, the SCSI I/O signal must be inactive to assert the SODL contents onto the SCSI bus. When the LSI53C825A is a target, the SCSI I/O signal must be active to assert the SODL contents onto the SCSI bus. The contents of the ...
Page 112
... If the LSI53C825A is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C825A does not halt the SCSI transfer when SATN parity error is received. Connected This bit is automatically set any time the LSI53C825A is connected to the SCSI bus as an initiator target ...
Page 113
... Control Zero (SCNTL0) selection before setting this bit. Arbitration is retried until won. At that point, the LSI53C825A holds BSY and SEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is reset automatically when the selection or reselection sequence is completed, or times out. ...
Page 114
... Using chained mode facilitates partial receive transfers and allows correct partial send behavior. When this bit is set and a data transfer ends on an odd byte boundary, the LSI53C825A stores the last byte in the SCSI Wide Residue (SWIDE) receive operation the ...
Page 115
... SLPMD SLPAR Mode If this bit is clear, the register functions like the LSI53C825. If this bit is set, the SLPAR register reflects the high or low byte of the SLPAR word, depending on the state of (SCNTL2), bit 4. It also allows a seed value to be written ...
Page 116
WSR Register: 0x03 (0x83) SCSI Control Three (SCNTL3) Read/Write SCF[2:0] 4-28 Registers count if the first byte received is one of the standard group codes. If this bit is set, the device does not reload the ...
Page 117
Note: For additional information on how the synchronous transfer rate is determine, refer to tion.” EWS Enable Wide SCSI When this bit is cleared, all information transfer phases are assumed to be eight bits, transmitted on SD[7:0]/ and SDP0/. When ...
Page 118
... Note that the LSI53C825A does not automatically reconfigure itself to the initiator mode as a result of being reselected. Enable Response to Selection When this bit is set, the LSI53C825A is able to respond to bus-initiated selection at the chip ID in the ID Zero (RESPID0) and registers. Note that the LSI53C825A does not automatically reconfi ...
Page 119
... LSI53C825A when sending synchronous SCSI data in either the initiator or target mode. These bits control the programmable dividers in the chip. TP2 The synchronous transfer period the LSI53C825A should use when transferring SCSI data is determined in the following example: Operating Registers Lowest MO[4:0] 0 ...
Page 120
... Registers The LSI53C825A is connected to a hard disk which can transfer data at 10 Mbytes/s synchronously. The LSI53C825A SCLK is running at 40 MHz. The synchronous transfer period (SXFERP) is found as follows: SXFERP = Period/SSCP + ExtCC Period = 1 Frequency = 1 SSCP = 1 SSCF = 1 40 MHz = 25 ns (This SCSI synchronous core clock is determined in ...
Page 121
Table 4.4 and combinations. Table 4.4 SCSI CLK CLK SCNTL3 (MHz) Bits [6:4] XFERP 66.67 3 66. 37.50 1.5 33.33 1 16.67 1 Table 4.5 SCSI CLK CLK SCNTL3 ...
Page 122
... Table 4.6 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C825A. These bits determine the LSI53C825A method of transfer for Data In and Data Out phases only; all other information transfers occur asynchronously. Table 4.6 Maximum Synchronous Offset ...
Page 123
Register: 0x06 (0x86) SCSI Destination ID (SDID) Read/Write Reserved ENC[3:0] Encoded Destination SCSI ID Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. ...
Page 124
... If the pin is pulled low externally, the board will be configured by SDMS software as a differential board pulled high or left floating, SDMS software will configure board. The LSI Logic PCI to SCSI host adapters use the GPIO4 pin in the process of flashing a new SDMS software ROM. ...
Page 125
... SCSI First Byte Received This register contains the first byte received in any asynchronous information transfer phase. For example, when a LSI53C825A is operating in the initiator mode, this register contains the first byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the fi ...
Page 126
... This register is used primarily for diagnostic testing or programmed I/O operation controlled by the SCRIPTS processor when executing SCSI SCRIPTS. transferring data using programmed I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the LSI53C825A starts executing normal SCSI SCRIPTS. 4-38 Registers 6 5 ...
Page 127
... Reserved ENID[3:0] Encoded Destination SCSI ID Reading the immediately after the LSI53C825A is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification. This condition is detected by examining the VAL bit above ...
Page 128
... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C825A stack interrupts). The DIP bit in the Interrupt Status (ISTAT) DMA interrupt conditions individually through the (DIEN) register ...
Page 129
... MDPE Master Data Parity Error This bit is set when the LSI53C825A as a master detects a data parity error target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of (CTEST4)). BF Bus Fault This bit is set when a PCI bus fault condition is detected. ...
Page 130
... Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) LSI53C825A is in target mode. During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set. ...
Page 131
Register: 0x0D (0x8D) SCSI Status Zero (SSTAT0) Read Only ILF ORF OLF ILF SIDL Least Significant Byte Full This bit is set when the least significant byte in the Input Data Latch (SIDL) transferred ...
Page 132
... FIFO Flags These four bits, along with bit 4, define the number of bytes or words that currently reside in the LSI53C825A SCSI synchronous data FIFO. These bits are not latched and they will change as data moves through the FIFO. register must be full Interrupt Status ...
Page 133
FF4 (SSTAT2 bit SDP0L Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched in the ...
Page 134
Register: 0x0F (0x8F) SCSI Status Two (SSTAT2) Read Only 7 ILF 0 ILF1 ORF1 OLF1 4-46 Registers initiator or target mode. These bits are set when the corresponding signal is active. They are useful when operating in the low level ...
Page 135
... SCSI Control One detect the case in which a target device disconnects, and then some SCSI device selects or reselects the LSI53C825A. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in (SCNTL1) is off. This bit is cleared when a Block Move ...
Page 136
... Abort Operation Setting this bit aborts the current operation under execution by the LSI53C825A. If this bit is set and an interrupt is received, clear this bit before reading the Status (DSTAT) register to prevent further aborted interrupts from being generated. The sequence to abort any operation is: 1 ...
Page 137
... SEM Semaphore The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C825A is executing a SCRIPTS operation. This bit enables the LSI53C825A to Operating Registers Interrupt Status (ISTAT) register. or ...
Page 138
... It is set after successfully completing selection or when the LSI53C825A responds to a bus-initiated selection or reselection also set after the SCSI function wins arbitration when operating in low level mode. When this bit is cleared, the LSI53C825A is not connected to the SCSI bus. Interrupt-on-the-Fly This bit is asserted by an INTFLY instruction during SCRIPTS execution ...
Page 139
... SCSI Interrupt Status One (SIST1) DIP DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C825A. The following conditions cause a DMA interrupt to occur: A PCI parity error is detected A bus fault is detected An abort condition is detected A SCRIPTS instruction is executed in single step ...
Page 140
... Registers FMT Byte Empty in DMA FIFO This was a general purpose read/write register in previous LSI53C8XX family chips. Although it is still a read/write register, LSI Logic reserves the right to use these bits for future LSI53C8XX family enhancements. FMT[3: Byte Empty in DMA FIFO These bits identify the bottom bytes in the DMA FIFO that are empty ...
Page 141
Register: 0x1A (0x9A) Chip Test Two (CTEST2) Read/Write DDIR SIGP CIO DDIR Data Transfer Direction This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred ...
Page 142
... This bit indicates the status of the LSI53C825A internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C825A. When this bit is set, TEOP is active. When this bit is cleared, TEOP is inactive. Data Request Status This bit indicates the status of the LSI53C825A internal Data Request signal (DREQ) ...
Page 143
... Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared. Any data in the FIFO is lost. After the LSI53C825A successfully clears the appropriate FIFO pointers and registers, this bit automatically clears. Note: This bit does not clear the data visible at the bottom of the FIFO ...
Page 144
... Pointer (DSP) register when a Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C825A is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate. BO ...
Page 145
... BDIS Burst Disable When set, this bit causes the LSI53C825A to perform back to back cycles for all transfers. When this bit is cleared, back to back transfers for opcode fetches and burst transfers for data moves are performed. Operating Registers register from the 7-bit value of DMA FIFO (DFIFO) register ...
Page 146
... Setting this bit causes the LSI53C825A to place all output and bidirectional pins into a high impedance state. In order to read data out of the LSI53C825A, this bit must be cleared. This bit is intended for board level testing only. Do not set this bit during normal system operation. ...
Page 147
FBL[2:0] FIFO Byte Control FBL3 FBL2 These bits steer the contents of the (CTEST6) register to the appropriate byte lane of the 64-bit DMA FIFO. If the FBL3 bit is ...
Page 148
... DMA FIFO appears as only 88 bytes deep. When set, the DMA FIFO size increases to 536 bytes. Using an 88-byte FIFO allows software written for other LSI53C8XX family chips to properly calculate the number of bytes residing in the chip after a target disconnect. The default value of this bit is zero. ...
Page 149
Register: 0x23 (0xA3) Chip Test Six (CTEST6) Read/Write DMA FIFO Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test ...
Page 150
... Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DMA Byte Counter (DBC) interrupt occurs if the LSI53C825A is not in the target mode, Command phase. The DMA Byte Counter (DBC) hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during table indirect I/O SCRIPTS ...
Page 151
... DNAD Operating Registers DCMD DMA Command This 8-bit register determines the instruction for the LSI53C825A to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set.” DNAD DMA Next Address This 32-bit register contains the general purpose address pointer ...
Page 152
Registers: 0x2C–0x2F (0xAC–0xAF) DMA SCRIPTS Pointer (DSP) Read/Write DSP Registers: 0x30–0x33 (0xB0–0xB3) DMA SCRIPTS Pointer Save (DSPS) Read/Write ...
Page 153
... This value is also independent of the width ( bits) of the data transfer on the PCI bus. The LSI53C825A asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data. Bus Request (REQ/) is ...
Page 154
... Command. If this bit is set, then the destination address is in I/O space; and if cleared, then the destination address is in memory space. This function is useful for memory-to-register operations using the Memory Move instruction when a LSI53C825A is I/O mapped. Bits 4 and 5 of the (CTEST2) register are used to determine the confi ...
Page 155
... These conditions are described in “Signal Descriptions.” BOF Burst Opcode Fetch Enable Setting this bit causes the LSI53C825A to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a memory-to-memory move type, the third Dword is accessed in a subsequent bus ownership ...
Page 156
... The LSI53C825A IRQ/ output is latched; once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. Masking an interrupt after the IRQ/ output is asserted does not cause IRQ deasserted ...
Page 157
... PCI contains the smaller value. Clearing this bit disables the cache line size logic and the LSI53C825A monitors the cache line size using the PFF Prefetch Flush Setting this bit causes the prefetch unit to flush its contents. This bit clears after the fl ...
Page 158
... When the LSI53C825A is executing SCRIPTS in manual start mode, the Start DMA bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. When the LSI53C825A is in single step mode, set the Start DMA bit to restart execution of SCRIPTS after a single step interrupt. ...
Page 159
... For more information on interrupts see Description.” Operating Registers LSI53C700 Family Compatibility When the COM bit is cleared, the LSI53C825A behaves in a manner compatible with the LSI53C700 family; selection/reselection IDs are stored in both the Selector ID (SSID) and registers. ...
Page 160
... Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. Reselected Indicates the LSI53C825A is reselected by a SCSI target device. Set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register for this to occur. SCSI Gross Error ...
Page 161
... SRST/ pulse. PAR SCSI Parity Error Indicates detection by the LSI53C825A of a parity error while receiving or sending SCSI data. See the Disable Halt on Parity Error or SATN/ Condition bits in the Control One (SCNTL1) when this condition is actually raised. ...
Page 162
... Enable Zero (SIEN0) 4-74 Registers Reserved Selection or Reselection Time-out The SCSI device which the LSI53C825A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) information on the time-out timer. General Purpose Timer Expired The general purpose timer is expired ...
Page 163
... ID) for the LSI53C825A to respond to reselection attempts. SGE SCSI Gross Error This bit is set when the LSI53C825A encounters a SCSI Gross Error Condition. The following conditions can result in a SCSI Gross Error Condition: Data Underflow – reading the SCSI FIFO when no data is present ...
Page 164
... FIFO. Unexpected Disconnect This bit is set when the LSI53C825A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C825A operates in the initiator mode. ...
Page 165
... Reading the SIST1 clears the interrupt condition. R Reserved STO Selection or Reselection Time-Out The SCSI device which the LSI53C825A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) information on the time-out timer. ...
Page 166
Register: 0x44 (0xC4) SCSI Longitudinal Parity (SLPAR) Read/Write 7 x SLPAR 4-78 Registers SLPAR SCSI Longitudinal Parity The SCSI Longitudinal Parity (SLPAR) of two multiplexed bytes; other register bit settings determine what is displayed at this ...
Page 167
Data Bytes – 00000000 1. 11001100 11001100 (XOR of word 1) 2. 01010101 10011001 (XOR of word 1 and 2) 3. 00001111 10010110 (XOR of word 1, 2 and 3) Even parity >>> 10010110 4. 10010110 00000000 A one in ...
Page 168
Register: 0x46 (0xC6) Memory Access Control (MACNTL) Read/Write 7 0 TYP[3:0] DWR DRD PSCPT SCPTS 4-80 Registers Wide Residue message is received. It may also be an overrun data byte. The power-up value of this register is indeterminate ...
Page 169
Register: 0x47 (0xC7) General Purpose Pin Control (GPCNTL) Read/Write This register is used to determine if the pins controlled by the Purpose (GPREG) register are inputs or outputs. Bits [4:0] in ...
Page 170
Register: 0x48 (0xC8) SCSI Timer Zero (STIME0) Read/Write 7 0 HTH[3:0] 4-82 Registers 4 3 HTH[3: Handshake-to-Handshake Timer Period These bits select the handshake-to-handshake time-out period, the maximum time between SCSI handshakes (SREQ/ to SREQ/ in ...
Page 171
Table 4.7 HTH[7:4], SEL[3:0], 1 GEN[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1. These values are correct if the CCF bits in the Three (SCNTL3) combinations in the bit description. ...
Page 172
Register: 0x49 (0xC9) SCSI Timer One (STIME1) Read/Write HTHBA GENSF 4-84 Registers HTHBA GENSF HTHSF Reserved Handshake-to-Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing ...
Page 173
Table 4.8 HTH[7:4], SEL[3:0], GEN[3:0] 1101 1110 1111 1. These values are correct if the CCF bits in the Control Three (SCNTL3) valid combinations in the bit description MHz clock is not supported for Ultra2 SCSI operation. HTHSF ...
Page 174
Register: 0x4A (0xCA) Response ID Zero (RESPID0) Read/Write 7 x RESPID0 Register: 0x4B (0xCB) Response ID One (RESPID1) Read/Write 15 x RESPID1 4-86 Registers Response ID Zero RESPID0 and Response ID One (RESPID1) selection or ...
Page 175
... IDs that could be used to select the LSI53C825A. During a SCSI selection or reselection phase when a valid ID is put on the bus, and the LSI53C825A responds to that ID, the “selected as” written into these bits. These bits are used with Response ID One (RESPID1) to multiple IDs on the bus ...
Page 176
... MHz external SCLK must be provided. SCSI Isolation Mode This bit allows the LSI53C825A to put the SCSI bidirectional and input pins into a low power mode when the SCSI bus is not in use. When this bit is set, the SCSI bus inputs are logically isolated from the SCSI bus ...
Page 177
... Setting this bit allows assertion of all SCSI control and data lines through the and SCSI Output Data Latch (SODL) of whether the LSI53C825A is configured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus included for diagnostic purposes only ...
Page 178
... SCSI Low level Mode Setting this bit places the LSI53C825A in low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be performed by setting the start sequence bit as described in the Control Zero (SCNTL0) register ...
Page 179
... When operating in a differential environment or at Fast SCSI timings, TolerANT Active negation should be enabled to improve setup and deassertion times. Active negation is disabled after reset or when this bit is cleared. For more information on LSI Logic TolerANT technology, see Chapter 1, “Introduction.” STR ...
Page 180
... STW 4-92 Registers Disable Single Initiator Response If this bit is set, the LSI53C825A ignores all bus-initiated selection attempts that employ the single-initiator option from SCSI-1. In order to select the LSI53C825A while this bit is set, the LSI53C825A SCSI ID and the initiator’s SCSI ID must both be asserted. Assert this bit in SCSI-2 systems so that a single bit error on the SCSI bus is not interpreted as a single initiator response ...
Page 181
... SCSI bus can be read from this register. Data can be written to the Latch (SODL) LSI53C825A by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs ...
Page 182
Registers: 0x54–0x55 (0xD4–0xD5) SCSI Output Data Latch (SODL) Read/Write SODL Registers: 0x58–0x59 (0xD8–0xD9) SCSI Bus Data Lines (SBDL) Read Only SBDL 4-94 Registers SODL SCSI Output Data ...
Page 183
... SCRATCHB Registers: 0x60–0x7F (0xE0–0xFF) Scratch Registers C–J (SCRATCHC–SCRATCHJ) Read/Write These registers are general purpose scratch registers for user defined functions. The LSI53C825A cannot fetch SCRIPTS instructions from this location. The power-up value of these registers is indeterminate. Operating Registers SCRATCHB x ...
Page 184
Registers ...
Page 185
... Chapter 5 SCSI SCRIPTS Instruction Set After power-up and initialization of the LSI53C825A, the chip can be operated in the low level register interface mode or in the high level SCSI SCRIPTS mode. Chapter 5 is divided into the following sections: Section 5.1, “Low Level Register Interface Mode” ...
Page 186
... Then, the start address of the next SCRIPTS instruction may be written to the to restart the automatic fetching and execution of instructions. The SCSI SCRIPTS mode of execution allows the LSI53C825A to make decisions based on the status of the SCSI bus, which offloads the microprocessor from servicing the numerous interrupts inherent in I/O operations ...
Page 187
... SCRIPTS Instructions Description Block Move instruction moves data between the SCSI bus and memory. I/O or Read/Write instructions cause the LSI53C825A to trigger common SCSI hardware sequences move registers. Transfer Control instruction allows SCRIPTS instructions to make decisions based on real time SCSI bus conditions ...
Page 188
... DMA FIFO for transfer to memory. At this point, the LSI53C825A requests use of the PCI bus again to transfer the data. When the LSI53C825A is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then releases the PCI bus ...
Page 189
... Wail disconnect alt2 Int 10 Table byte count address byte count address byte count address byte count address Message Buffer Command Buffer Data Buffer Status Buffer High Level SCSI SCRIPTS Mode Write DSA S Write Y DSP Fetch SCRIPTS U LSI53C825A SCSI Bus S Data 5-5 ...
Page 190
Block Move Instructions Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the Mode (DMODE) address resides in memory or I/O space. When data is ...
Page 191
... Once the data pointer address is loaded executed as when the chip operates in the direct mode. This indirect feature allows a table of data buffer addresses to be specified. Using the LSI Logic SCSI SCRIPTS assembler, the table offset is placed in the script at compile time. Then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor ...
Page 192
... A subsequent fetch from that address brings the data values into the chip. For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C825A. Execution of the move begins at this point. Data Structure Address ...
Page 193
... MOVE 1 CHMOV These instructions perform the following steps: 1. The LSI53C825A verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C825A asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as defined by the Phase Field bits in the instruction. ...
Page 194
... DMA Byte Counter (DBC) If the DMA Byte Counter (DBC) 0x000000, an illegal instruction interrupt is generated. 4. The LSI53C825A transfers the number of bytes specified in the DMA Byte Counter (DBC) starting at the address specified in the Address (DNAD) register. If the Opcode bit is set and ...
Page 195
... CHMOV 1 MOVE These instructions perform the following steps: 1. The LSI53C825A verifies that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C825A waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C825A has not yet transferred data by responding with a SACK/ ...
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... Set ATN instruction), the LSI53C825A deasserts SATN/ during the final SREQ/SACK/ handshake. 7. When the LSI53C825A is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction. ...
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... This process is repeated until the register is decremented to zero. At this time, the LSI53C825A fetches the next instruction. If bit 28 is set, indicating table indirect addressing, this field is not used. The byte count is instead fetched from a table pointed to by the Data Structure Address (DSA) register ...
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I/O Instruction I/O Instructions perform the following SCSI operations in Target and Initiator mode. These I/O operations are chosen with the opcode bits in the DMA Command (DCMD) OPC2 This section describes these I/O ...
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... If the LSI53C825A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the Manually set the LSI53C825A to Initiator mode reselected Target mode selected. Disconnect Instruction The LSI53C825A disconnects from the SCSI bus by deasserting all SCSI signal outputs ...
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... Note: Note: 5-16 SCSI SCRIPTS Instruction Set Wait Select Instruction 1. If the LSI53C825A is selected, it fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP reselected, the LSI53C825A fetches the next instruction from the address pointed to by the 32-bit jump address fi ...