LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 146

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-58
ZMOD
ZSD
SRTM
MPEE
Registers
High Impedance Mode
Setting this bit causes the LSI53C825A to place all output
and bidirectional pins into a high impedance state. In
order to read data out of the LSI53C825A, this bit must
be cleared. This bit is intended for board level testing
only. Do not set this bit during normal system operation.
SCSI Data High Impedance
Setting this bit causes the LSI53C825A to place the SCSI
data bus SD[15:0] and the parity lines SDP[1:0] in a high
impedance state. In order to transfer data on the SCSI
bus, clear this bit.
Shadow Register Test Mode
Setting this bit allows access to the shadow registers
used by Memory-to-Memory Move operations. When this
bit is set, register accesses to the
Data Structure Address (DSA)
the shadow copies STEMP (Shadow TEMP) and SDSA
(Shadow DSA). The registers are shadowed to prevent
them from being overwritten during a Memory-to-Memory
Move operation. The
Temporary (TEMP)
used for table indirect calculations, and the address
pointer for a call or return instruction, respectively. This bit
is intended for manufacturing diagnostics only and should
not be set during normal operations.
Master Parity Error Enable
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C825A. A parity error during a bus
master write is detected by the target, and the
LSI53C825A is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C825A does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
registers contain the base address
Data Structure Address (DSA)
registers are directed to
Temporary (TEMP)
and
and
6
5
4
3